CDM tests on interface test chips for the verification of ESD protection concepts

Brodbeck, T.; Esmark, K.; Stadler, Wolfgang

doi:10.1109/eosesd.2007.4401725

Cited by 14 publications

(5 citation statements)

References 2 publications

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“…Electrostatic discharge (ESD) damage modes can be classified using the human-body model (HBM) (2), machine model (MM) (3) and charged device model (CDM) (4). As the MOS devices are scaled down to 0.5 m or smaller, the lightly-doped drain (LDD) ion (5) and the silicide engineering (6)(7) are applied to reduce the hot-carrier effect (8) and the sheet resistance of source and drain to increase the MOS transistor switching speed, weakening the immunity against ESD.…”

Section: Fundamental Of Esd and Esd Damage On Mos Devicesmentioning

confidence: 99%

Promotion of ESD-CDM Immunity in Dicing Saw Process

Wang

Huang²,

Hsieh

et al. 2008

ECS Trans.

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Polyimide (PI) dielectric as a heatproof material is popularly adopted in integrated circuit (IC) industry. In assembly dicing saw process, the de-ionized (D.I.) water shows the higher resistance and rubs with PI material. Therefore, the negative electrostatic charges are generated and accumulated to gate oxide capacitor or p-n junction capacitor in IC chips. Because the discharge path is isolated in this time, the sufficiently cumulative charges will damage the IC devices in this process step. These damaged ICs demonstrate the function fail. To overcome this failure mechanism, an adequate amount of CO2 gas flow and some suitable control of water pressure were studied. Through this effort, the final-test yield in sub-micron or deep-submicron analog power complementary metal-oxide-semiconductor (CMOS) ICs was impressively promoted from 80% to 98%.

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Section: Fundamental Of Esd and Esd Damage On Mos Devicesmentioning

confidence: 99%

Promotion of ESD-CDM Immunity in Dicing Saw Process

Wang

Huang²,

Hsieh

et al. 2008

ECS Trans.

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“…While standardized field-induced CDM (FICDM) is the default CDM testing/stress method [12,23], transmission line pulsing (TLP) IV characterization reports have also been used for CDM purposes [17,23] Previous works show a variety of different methods to try to overcome the issues caused by CDM. Some findings argue the importance of the packaging on CDM occurrence (pin count, die area, metal frame structure [24]) by presenting their findings in terms of CDM peak currents dependence of various packages [18,23,27] or by trying to model the package parameters into software scripts to be used during pre-silicon testing simulation steps [15,20,26]. Similarly, a number of previously published works discuss the possibility of full-chip simulations [10,[16][17][18].…”

Section: Introductionmentioning

confidence: 99%

CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Dobre

Coll²,

Brezeanu

2021

Electronics

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This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

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confidence: 99%

“…Introduction: Gate-oxide damage is a typical failure mode in input buffer circuits, and is caused by the charged device model (CDM) test [1][2][3][4][5]. This phenomenon is often explained by the fact that there is too large a voltage drop across the gate oxide owing to the high CDM current flowing through the bus line and the protection device [1,3]. However, the oxide damage is caused by the current flowing into the gate oxide based on the time before the oxide breakdown model, TBD = (N BD /k) 1/m /J h [6], where N BD is the critical trap density, k is the lattice-hole generation coefficient and J h is the tunnel current density for the hole.…”

mentioning

confidence: 99%

“…One is the body and the other is the source. Up to now, most experimental results for the CDM where the gate oxide damage is induced on the input buffer are based on low-voltage (LV) CMOS technologies since the transistor is more susceptible to the CDM stress [1][2][3][4][5]. For the first time, the manner in which the CDM current flows through the two terminals before the oxide damage is induced is explored.…”

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confidence: 99%

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Failure mechanism for input buffer under CDM test

et al. 2014

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The influence of the body layout on the charged device model (CDM) failure site and the robustness of the input buffer is explored. The failure analysis results confirm that the gate oxide is damaged. The failure site can be moved from the region above the channel to the overlap region between the source and the gate once the body layout is cut from a ring into a small segment, providing direct evidence demonstrating that the CDM current flows through the gate oxide via the body and the source of the transistor, since both connect to the Vss bus line. Otherwise, changing the body layout of the input buffer transistor does not vary the failure location.

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CDM tests on interface test chips for the verification of ESD protection concepts

Cited by 14 publications

References 2 publications

Promotion of ESD-CDM Immunity in Dicing Saw Process

Promotion of ESD-CDM Immunity in Dicing Saw Process

CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Failure mechanism for input buffer under CDM test

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