CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication

Wang, Mu‐Chun; Yang, Hsin-Chia; Liao, Wen‐Shiang; Yang, Hsiu-Yen; Hoe, Yao-Yuan; Lin, Kuang-Hung; Chen, Shuang-Yuan

doi:10.1109/isne.2010.5669140

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…Two different splits were analyzed, one with unstrained silicon that is used as a reference, and the second uniaxially strained one employing a dual contact etch stop layer technique [11], generating tensile stress for nMuGFETs and compressive stress for pMuGFETs.…”

Section: Device Characteristicsmentioning

confidence: 99%

Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation

Bordallo¹,

Teixeira²,

Silveira³

et al. 2014

Semicond. Sci. Technol.

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The influence of x-ray irradiation on the main digital and analog parameters of triple gate siliconon-insulator FinFETs is investigated for unstrained and uniaxially strained devices. Comparing the p-and n-MuGFET response to radiation, x-rays can be more harmful for nMuGFETs than for the p-type counterparts due to the back-interface leakage current, which is generated by the positive charges trapped in the buried oxide. However, in pMuGFETs, the radiation tends to suppress the parasitic back-conduction, resulting in an improvement of the device performance.

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Section: Device Characteristicsmentioning

confidence: 99%

Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation

Bordallo¹,

Teixeira²,

Silveira³

et al. 2014

Semicond. Sci. Technol.

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“…After etching and defining the gate poly-silicon, a 50 nm TEOS film is deposited for forming the sidewall spacer. Specific silicon nitride is deposited by plasma enhanced chemical vapor deposition (PECVD) [5] covering the whole device as the contact etching stop layer and providing the compressive (-2.0GPa) strain to the devices.…”

Section: Process Establishment and Measurement Conditionsmentioning

confidence: 99%

Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

Wang

Peng

Wang

et al. 2013

2013 International Symposium on Next-Generation Electronics

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Increasing the electrical performance of the MOSFETs with contact etch stop layer (CESL) and SiGe channel technologies in strain engineering is indeed approached. Using silicon capping layer performs the benefits on the smoothness of channel surface and the prevention of germanium penetration from SiGe layer. In this study, the deposited capping layer thicknesses with SiGe channel of (110) substrate wafer were 1.5 and 3.0 nm on the poly gate. The interesting device parameters including drive current, transconductance, threshold voltage (V T ) and subthreshold swing (S.S.) with temperature effect are systematically analyzed.

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CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication

Cited by 2 publications

References 8 publications

Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation

Analog performance of standard and uniaxial strained triple-gate SOI FinFETs under x-ray radiation

Si-capping thicknesses impacting compressive strained MOSFETs with temperature effect

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