Challenges and design choices in nanoscale CMOS

Abstract

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In this article, we will first review the history of technology scaling that follows Moore's law from the prespective of microprocessor designs. Challenges to continue the historical scaling trends will be highlighted and design choices to address two specific challenges, process variation and leakage power, will be discussed. In nanoscale CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in process variation and the resulting increase in design margins. Concept of adaptive circuit schemes to deal with increasing design margins will be explained. Next, with threshold voltage scaling, subthreshold leakage power has become a significant portion of total power in nanoscale CMOS systems. Therefore, it has become imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and circuit techniques to reduce system leakage will be discussed. It is essential to point out that this article does not cover all challenges that nanoscale CMOS systems face. Challenges that are not detailed in the main sections of the article and speculation on what future nanoscale silicon based CMOS systems might resemble are summarized.

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

“…This results in reduced threshold voltage. In short channel transistor, the barrier height and therefore the threshold voltage are a strong function of the drain voltage [4]. As Figure 1 indicates, the barrier reduces as the drain voltage is increased.…”

“…Drain-induced barrier lowering (DIBL) reduces threshold voltage for short channel devices and increases threshold voltage roll-off. For short channel devices, channel length variation (ΔL) translates to threshold voltage variation (ΔV th ) [4]. DIBL occurs when the depletion region of the drain interacts with the source near the channel…”

“…Figure 10: Barrier lowering (BL) resulting in threshold voltage rolloff with channel length reduction [4].…”

“…The exponential relation between the driving voltage on the gate and the drain current is a straight line in a semilog plot. Figure 11: Schematic log I ON -V g characteristics to show the factor affecting power consumption [4].…”

Statistical Approach for Yield Optimization for Minimum Energy Operation in Subthreshold Circuits Considering Variability Issues

“…With leakage power becoming a significant contributor to total power dissipation, leakage current flowing through the grid can result in significant supply-voltage drops. The increase in the current density with the scaling in the technology and increase in rate of switching make it more challenging to retain the traditional bound on the supply-voltage noise [6]. Device threshold voltage is dependent on a number of process parameters such as channel doping concentration and gate length.…”