Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

Abstract

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

Point-defect management in homoepitaxially grown Si-doped GaN by MOCVD for vertical power devices

“…4,5) The development of thick n-GaN drift layers with controllable doping in the range of 10 15 -10 16 cm −3 is the key to the realization of kV-class, GaN-based power devices. 6) Although quasi-vertical devices based on heteroepitaxially-grown GaN epilayers on SiC, sapphire, and Si (111) 4,5,7) have been demonstrated for <1 kV breakdown voltage, these epi-stacks exhibit high threading dislocation densities, exceeding 10 8 cm −2 , thereby, deleteriously impacting the device lifetime and performance both in the ON and OFF states. While the screw dislocations enhance the reverse leakage, 8) threading edge dislocations induce electron traps, at about every c-lattice translation.…”

Study and characterization of GaN MOS capacitors: Planar vs trench topographies

“…All the structures have a bilayer dielectric stack composed of an interfacial 2.5 nm layer of Al2O3, and a bulk SiO2 layer of 50 nm, deposited on the top n + GaN layer. The bilayer configuration is advantageous in trench MOSFETs as reported in previous works 10,11 , as the ALD-deposited thin dielectric ensures a high-quality interface with GaN, while the thick SiO2 improves the gate dielectric stack robustness. While emulating the behavior of unit gate cells of a trench power MOSFET, the larger area (= 7.25 × 10 -4 cm 2 ) of the test capacitors allows for improved resolution and diagnostic validity of the measured data.…”

“…First, a bulk GaN removal step was implemented using a Cl2/Ar chemistry. Secondly, Atomic Layer Etch (ALE) processing steps are implemented as a soft landing step 11 . Before the dielectric deposition is done, wet cleaning steps are implemented to clean up organic residues.…”

Impact of doping and geometry on breakdown voltage of semi-vertical GaN-on-Si MOS capacitors

“…Among all the different architectures, trench-gate MOSFETs on foreign substrates are promising candidates for the realization of high power and high frequency switches, thanks to their economic advantages with respect to native substrates [7]. Nonetheless, heteroepitaxial vertical and semivertical GaN technology is in a nascent stage and several problematic issues have to be fully investigated for the realization of high-quality devices [8].…”