Challenges for 3D IC integration: bonding quality and thermal management

Leduc, P.; Sillon, N.; Maîtrejean, S.; Louis, D.; Passemard, G.; Crecy, F. de; Fayolle, M.; Charlet, B.; Enot, T.; Zussy, M.; Jones, Bob; Barbé, Jean-Charles; Kernevez, N.

doi:10.1109/iitc.2007.382392

Cited by 74 publications

(25 citation statements)

References 5 publications

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“…This assumption may lead to strongly underestimated maximum temperature. Thus, several authors [31] use this simplification but perform detailed simulation of ISBN: 978-2-35500-010-2 7-9 October 2009, Leuven, Belgium 3D thermal effects due to the presence and localization of supervias, and analyze the local (3D) and global (1D) modeling contribution to the maximum temperature, showing that thermal resistance can be higher than 1D thermal resistance due to local 3D effects and even more fine-grain transient analysis need to be performed to avoid thermal overestimations. Finally, numerical thermal simulations have been carried out to convert power dissipation distribution into a temperature distribution in a 3D IC [32].…”

Section: Related Workmentioning

confidence: 99%

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Valle

Atienza

2011

Microelectronics Journal

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Abstract-New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute multiple applications (games, video), while meeting additional design constraints (energy consumption, time-to-market, etc.). Moreover, the rise of temperature in the die for MPSoCs, especially for forthcoming 3D chips, can seriously affect their final performance and reliability. In this context, transient thermal modeling is a key challenge to study the accelerated thermal problems of MPSoC designs, as well as to validate the benefits of active cooling techniques (e.g., liquid cooling), combined with other state-of-the-art methods (e.g., dynamic frequency and voltage scaling), as a solution to overcome run-time thermal runaway.In this paper, I present a novel approach for fast transient thermal modeling and analysis of 2D/3D MPSoCs with active cooling, which relies on the exploitation of combined hardwaresoftware emulation and linear thermal models for liquid flow. The proposed framework uses FPGA emulation as the key element to model the hardware components of 2D/3D MPSoC platforms at multi-megahertz speeds, while running real-life software multimedia applications. This framework automatically extracts detailed system statistics that are used as input to a scalable software thermal library, using different ordinary differential equation solvers, running in a host computer. This library calculates at run-time the temperature of on-chip components, based on the collected statistics from the emulated system and the final floorplan of the 2D/3D MPSoC. This approach creates a close-loop thermal emulation system that allows MPSoC designers to validate different hardware-and software-based thermal management approaches, including liquid cooling injection control, under transient and dynamic thermal maps. The experimental results with 2D/3D MPSoCs illustrate speed-ups of more than three orders of magnitude compared to cycle-accurate MPSoC thermal simulators, at the same time as preserving the accuracy of the estimated temperature within 3% of traditional approaches using finite-element simulations for 3D stacks and liquid cooling.

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Section: Related Workmentioning

confidence: 99%

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Valle

Atienza

2011

Microelectronics Journal

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“…Other works [23] analyze the local (3D) and global (1D) modeling contribution to the maximum temperature, showing that thermal resistance can be higher than 1D thermal resistance due to local 3D effects.…”

Section: Related Workmentioning

confidence: 99%

Thermal modeling and analysis of 3D multi-processor chips

2010

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“…Indeed, single chip can be stacked over another one in a die to die approach (D2D [6]) or over a wafer according to a die to wafer method (D2W [7,8]). Wafer to wafer bonding (W2W [9]) can be performed too, leading to a collective stacking of the whole embedded dies. Although W2W approach provides the highest production throughput and alignment accuracy, stacked dies must have the same size, reducing modular aspect of 3D integration, and potential non-functional dies from two wafers are heaped which hardly restricts final yield.…”

Section: Overview Of 3d Process Flowsmentioning

confidence: 99%

Integration and Frequency Dependent Parametric Modeling of Through Silicon via Involved in High Density 3D Chip Stacking

Cadix

Fuchs²,

Rousseau³

et al. 2010

ECS Trans.

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Evaluation of Through Silicon Via (TSV) electrical performance is hardly required today to improve heterogeneous 3D chip performance in the frame of a "more than Moore" approach. Accurate modeling of TSV is consequently essential to perform design optimizations and process tuning. This paper proposes a methodology based on RF characterizations and simulations, leading to a frequency dependent analytical model including MOS effect of high aspect ratio TSV. Specific test structures integrated on both floating Si bulk and CMOS 65 nm active wafers according to a face-to-face Via Last After Bonding process enable C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) and implemented in SPICE simulator to predict TSV impact on signal propagation.

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Challenges for 3D IC integration: bonding quality and thermal management

Cited by 74 publications

References 5 publications

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

Thermal modeling and analysis of 3D multi-processor chips

Integration and Frequency Dependent Parametric Modeling of Through Silicon via Involved in High Density 3D Chip Stacking

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