Challenges of ultimate ultra-fine pitch process with gold wire &amp;amp; copper wire in QFN packages

Tan, C. E.; Liong, J. Y.; Dimatira, Jeramie; Tan, Jason; Kok, Lee Wee

doi:10.1109/iemt.2014.7123107

Cited by 20 publications

(21 citation statements)

References 2 publications

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“…Copper wire also offers better or higher electrical conductivity (reciprocal of resistivity) than its Gold counterpart, allowing more signals to flow in the circuit with less electrical loss at a given time. The development of Copper wire is one important achievement in the semiconductor industry, providing costefficient devices for wide range of power applications [3][4]. Moreover, one critical part of the development is at the package feasibility level wherein package design, modeling, characterization, and simulation take important roles.…”

Section: Fig 1 Examples Of Package Electrical Modelingmentioning

confidence: 99%

“…4 illustrates the overview of the assembly wirebonding process. It is worth noting that wirebonding process varies also with the product and the technology [1,4,6]. Wirebonding could also be used to connect any semiconductor device or integrated circuit (IC) to other electronic device or to connect from one printed circuit board (PCB) to another.…”

Section: Wirebonding Process Overviewmentioning

confidence: 99%

“…However, in recent years the price of Gold has greatly increased, fueling the demand for high-volume wirebonding using Copper wire, which can lead to significant cost savings due to lower raw material cost. Aside from being cost-efficient, Copper wire exhibits lower resistance [3,4,7] in Fig. 5, which allows more signals to flow and less electrical loss at a given time.…”

Section: Copper Wire Versus Gold Wirementioning

confidence: 99%

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Wirebond Solution of Semiconductor IC Package through Modeling and Simulation

Gomez¹,

Moreno²,

Pulido³

2019

JERR

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This technical paper presents a study of wirebond selection highlighting the package electrical modeling and simulation done for semiconductor integrated circuit (IC) leadframe package (hereinafter referred to as Device Z) with different wirebond configurations: Gold 2N 1.3 mil, Gold 4N 1.3 mil, Copper 1.3 mil, Copper 1.2 mil, Copper 1.1 mil and Copper 1.0 mil. Package design, modeling and simulation are essentially important in the early stage of the package development, particularly at the package feasibility phase. As Device Z is previously assembled with Gold 4N 1.3 mil wirebond configuration, this technical paper focused in determining the best alternative for Gold 4N 1.3 mil in wirebonding through package modeling and simulation. Statistical analysis reinforced the study to verify the trend and to check if there is significant statistical difference in the resistance, inductance and capacitance (hereinafter referred to as RLC) performance of the device given the different wirebond configurations. Cost analysis was crucial to determine the cost impact of using different wires. Prioritizing the wirebond thickness and cost without sacrificing the electrical performance, Copper 1.1 mil would be the most suitable replacement for Gold 4N 1.3 mil wirebond configuration. However, since Copper 1.1 mil is not yet available in the market, Copper 1.2 mil could be used, with better electrical parameters. In addition, Copper wire offered significant cost improvement over its Gold counterpart. Computed cost per unit of Copper 1.3 mil is just 6% of the total cost of the Gold 4N 1.3 mil – that is 94% cost savings. Ultimately, Copper wire technology offers significant cost savings and could pave the way for more businesses in the plant.

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Section: Fig 1 Examples Of Package Electrical Modelingmentioning

confidence: 99%

Section: Wirebonding Process Overviewmentioning

confidence: 99%

Section: Copper Wire Versus Gold Wirementioning

confidence: 99%

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Wirebond Solution of Semiconductor IC Package through Modeling and Simulation

Gomez¹,

Moreno²,

Pulido³

2019

JERR

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“…The fast pace growth on IC package provides the need for every industry to come up with more innovative packaging solutions to stay competitive in the market. With new and continuous technology trends and breakthroughs, challenges in assembly manufacturing are inevitable [1][2][3][4][5]. In this paper, an advanced leadframe package was able to use solder paste material on the bottom area to provide the electrical connections, however, challenges were encountered.…”

Section: Introductionmentioning

confidence: 99%

Ball Misplace Mitigation through Process Optimization of Advanced Leadframe Package

Bacquian¹,

Gomez²,

Graycochea³

2020

JERR

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One of the challenging assembly processes in semiconductor manufacturing industry is stencil printing using solder paste as direct material. With this technology, some issues were encountered during the development phase of an advanced leadframe device and one of which is the solder ball misplace or off-centered ball. This paper, hence, focused on addressing the ball misplace issue at stencil printing process. Comprehensive parameter optimization particularly on the print speed and print force was employed to eliminate or significantly reduce the ball misplace defect at stencil printing process. With this process optimization and improvement, a reduction of around 96 percent ball misplace occurrence was achieved.

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“…The development of Copper (Cu) wire is the biggest leap today on the semiconductor industry providing cost efficient and high power devices [1][2][3]. Copper wire provides better conductivity than Gold (Au) and Aluminum (Al), in which helps offer a better heat dissipation and increased power ratings even with thinner wire application.…”

Section: Introductionmentioning

confidence: 99%

Challenges and Resolution for Copper Wirebonding on Tapeless Leadframe Chip-on-Lead Technology

Sumagpang¹,

Gomez²

2018

JERR

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This technical paper discusses a methodological and systematic way of resolving key challenges during introduction of Chip-On-Lead package specifically wirebonding issues that leads to production dilemma during production ramp-up of products using copper wire in tapeless leadframe. The project was intended to determine the “Red-X” or the major cause of yield detractors that may lead to quality issue during wirebonding process. Problem solving tools were showcased in this paper such as Data Analysis, Cause and Effect, Design-of–Experiment (DOE) and mechanical dimensional analysis which provided substantial impact in determining the real root-cause of the problem. Step-by-step elimination of variables was achieved with the use of statistical engineering tools. Outcome of the project eliminated the occurrence of Non-Stick-On-Pad (NSOP) during wirebonding process without cost involved and just optimizing the available in-house resources. The improvements also enhanced the quality of the product after final test which on the other hand lower the risk of having potential customer complaint in the future.

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Challenges of ultimate ultra-fine pitch process with gold wire & copper wire in QFN packages

Cited by 20 publications

References 2 publications

Wirebond Solution of Semiconductor IC Package through Modeling and Simulation

Wirebond Solution of Semiconductor IC Package through Modeling and Simulation

Ball Misplace Mitigation through Process Optimization of Advanced Leadframe Package

Challenges and Resolution for Copper Wirebonding on Tapeless Leadframe Chip-on-Lead Technology

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