This report of an atypical cause of bowel obstruction suggests that laparoscopic intervention may be successfully used in the diagnosis and treatment of traumatic diaphragmatic hernia.

New design for a certain issue in semiconductor industry is another way to modify the standard configuration into specified limit or to make a possible solution of the problem.  This paper presents a new modified design for wirebond top plate with a bias platform structure that will maintain a consistent second bond into a leadframe leads with half-etch configuration on quad-flat no-leads (QFN) packages especially in wirebond process. This paper used a side by side comparison to proof that the new design is better than the older design.  With the new specialized wire clamp and top plate design, parts per million (PPM) level performances is improved by almost 90%.

Wirebonding is one of the most challenging assembly manufacturing processes in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to mitigate misplaced ball issues and prevent pattern recognition alignment errors. Parameter optimization particularly on wirebond looping was done to ensure that the silicon die’s L-fiducial is visible and not obstructed by the wires, which is the operator point or die reference of the unit during wirebonding setup. Ultimately, the optimized wirebonding parameter prevented the pattern recognition alignment error and misplaced ball issues during the lot process.  For future works, the configuration and technique could be applied on packages with the similar situation.

This paper presents the modification and improvement done on the wire clamp and top plate (WCTP) design to eliminate the bouncing effect of the silicon die that leads to smashed ball reject during the formation of wire. The protrusion of the unit on the vacuum hole produced movement and slight vibration that affects the consistency of wirebonding. Through changing the standard vacuum hole to micro-holes provides underneath support to the unit and eliminates the overhanging or protrusion during the formation of wire. The implementation of the micro-hole design reduced the defect parts per million (dppm) occurrence to zero.

This paper presents the application of an innovative design of wirebond process plate during wirebonding process of thin semiconductor carrier such as the pre-encapsulated leadframe. The implementation of the specialized process plate aims to improve the conventional method of wirebonding from panel type to single-row design to reduce the occurrence of warpage on thin leadframes. In this study, an 85% reduction for warpage level is achieved after the introduction of the new design of process plate. Future works could use the improved process plate design for devices of similar configuration.