New design for a certain issue in semiconductor industry is another way to modify the standard configuration into specified limit or to make a possible solution of the problem. This paper presents a new modified design for wirebond top plate with a bias platform structure that will maintain a consistent second bond into a leadframe leads with half-etch configuration on quad-flat no-leads (QFN) packages especially in wirebond process. This paper used a side by side comparison to proof that the new design is better than the older design. With the new specialized wire clamp and top plate design, parts per million (PPM) level performances is improved by almost 90%.
In semiconductor packaging industry, silhouetted die defect is occasionally encountered in singulation process esp. on substrate land grid array (LGA) package with tight clearances. This paper is focused on the prevention of the silhouetted die occurrence as it would affect the assembly yield performance of the device. The silhouetted die is caused by the tight clearance of die edge to package edge, given the machine and process tolerances. Process enhancement and optimization were done through adjusting the die placement accordingly as per the defined measurement. Eventually, the occurrence of silhouetted die was successfully mitigated by formulating the appropriate die placement references.
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