Challenges of Using On-Chip Performance Monitors for Process and Environmental Variation Compensation

Zandrahimi, Mahroo; Al-Ars, Zaid; Debaud, Philippe; Castillejo, Armand

doi:10.3850/9783981537079_0796

Cited by 4 publications

(2 citation statements)

References 5 publications

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“…Notice that the variations introduced by the process can be classified in two types: i) The Inter-chip variations, that can be observed in terms of performance gaps between different devices, as shown in Fig. 8 ii) Intra-chip variations, as demonstrated by [21], resulting in different first N critical path, that can affect the consistency between the behaviour of the circuit and an on-chip performance monitor, confirmed also by our analysis. As for the temperature variation compensation, we derived a general correlation model between all the chips.…”

Section: Process Variationssupporting

confidence: 75%

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Mauro

Rossi

Pullini

et al. 2017

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Environmental temperature variations, as well as process variations, have a detrimental effect on performance and reliability of embedded systems implemented with deep-sub micron technologies. This sensitivity significantly increases in ultralow-power (ULP) devices that operate in near-threshold, due to the magnification of process variations and to the strong thermal inversion that affects advanced technology nodes. Supporting an extended range of reverse and forward body-bias, UTBB FD-SOI technology provides a powerful knob to compensate for such variations. In this work we propose a methodology to efficiently compensate, at run-time, these variations. The proposed method exploits on-line performance measurements by means of Process Monitoring Blocks (PMBs) coupled with on-chip low-power Body Bias Generators. We characterize the response of the PMBs versus the maximum achievable frequency of the system, deriving a predictive model able to estimate such frequency with an error of 3%. We apply this model to compensate Temperature-induced performance variations, estimating the maximum frequency with an error of 7%; we eliminate the error by adding an appropriate body-bias margin resulting in a worst case global power consumption overhead of 5%. As further improvement, we generalize the methodology to compensate also process variations, obtaining an error of 28% on the estimated maximum performance and compensating this error with an overhead of 17% on the global power consumption.

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Section: Process Variationssupporting

confidence: 75%

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Mauro

Rossi

Pullini

et al. 2017

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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“…-Not effective enough: since there are discrepancies in the responses of same PMBs from different test chips, the estimated correlation between the frequency of PMBs and the actual performance of the circuit could be very pessimistic, which results in wasting power and performance. In [21], a silicon measurement on 625 devices manufactured using 28nm FD-SOI technology had been done. 12 PMBs are embedded in each device.…”

Section: Motivationmentioning

confidence: 99%

Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

et al. 2019

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With the continued down-scaling of IC technology and increase in manufacturing process variations, it is becoming ever more difficult to accurately estimate circuit performance of manufactured devices. This poses significant challenges on the effective application of adaptive voltage scaling (AVS) which is widely used as the most important power optimization method in modern devices. Process variations specifically limit the capabilities of Process Monitoring Boxes (PMBs), which represent the current industrial state-of-the-art AVS approach. To overcome this limitation, in this paper we propose an alternative solution using delay testing, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS'99 benchmarks with 28nm FD-SOI library, that using delay test patterns result in an error of 5.33% for transition fault testing (TF), error of 3.96% for small delay defect testing (SDD), and an error as low as 1.85% using path delay testing (PDLY). In addition, the paper also shows the impact of technology scaling on the accuracy of delay testing for performance estimation during production. The results show that the 65nm technology node exhibits the same trends identified for the 28nm technology node, namely that PDLY is the most accurate, while, TF is the least accurate performance estimator.

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Industrial approaches for performance evaluation using on-chip monitors

Zandrahimi

Debaud

Castillejo

et al. 2016

2016 11th International Design &Amp; Test Symposium (IDT)

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Challenges of Using On-Chip Performance Monitors for Process and Environmental Variation Compensation

Cited by 4 publications

References 5 publications

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology

Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

Industrial approaches for performance evaluation using on-chip monitors

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