Channel masking synthesis for efficient on-chip test compression

Chickermane, V.; Foutz, B. E.; Keller, B.

doi:10.1109/test.2004.1386981

Cited by 108 publications

(42 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is the reason why the dual compression approach has been proposed in this thesis not only to enable the users to achieve higher test data volume compression ratio, but also to achieve diagnosability. Here, the Mask Registers are used to mask out unpredictable (X) response values before they enter the MISRs, which would cause their final signatures to become unpredictable [16].…”

Section: Streaming Outputsmentioning

confidence: 99%

“…Core-Masking logic includes only one register bit common to all MISR output and AND gates for individual MISR outputs. Core-Masking register bit is serially connected to the X-Masking registers (The number of X-Masking register bit is same as the number of scan channels) [16]. There is one mask bit for each MISR, so not much mask data is required.…”

Section: Application To Partial Good Chipsmentioning

confidence: 99%

See 1 more Smart Citation

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression

Uzzaman

Keller

Foutz

et al. 2010

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYThis paper describes a simple means to enable direct diagnosis by bypassing MISRs on a small set of tests (MISR-bypass test mode) while achieving ultimate output compression using MISRs for the majority of tests (MISR-enabled test mode.) By combining two compression schemes, XOR and MISRs in the same device, it becomes possible to have high compression and still support compression mode volume diagnostics. In our experiment, the MISR-bypass test was first executed and at 10% of the total test set the MISR-enabled test was performed. The results show that compared with MISR+XOR-based compression the proposed technique provides better volume diagnosis with slightly small (0.71 X to 0.97 X) compaction ratio. The scan cycles are about the same as the MISRenabled mode. A possible application to partial good chips is also shown.

show abstract

Section: Streaming Outputsmentioning

confidence: 99%

Section: Application To Partial Good Chipsmentioning

confidence: 99%

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression

Uzzaman

Keller

Foutz

et al. 2010

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

show abstract

“…Without the MUXes between MISRs and Space Compactor the configuration is a standard OPMISR+ scheme. The Mask Registers are used to mask out unpredictable (X) response values before they enter the MISRs, which would cause their final signatures to become unpredictable [10].…”

Section: Streaming Outputsmentioning

confidence: 99%

Optimizing Test Data Volume Using Hybrid Compression

Keller¹,

Bhatia

Bartenstein³

et al. 2008

2008 17th Asian Test Symposium

View full text Add to dashboard Cite

show abstract

“…Previously proposed schemes for blocking unknowns include the selective compactor [4], channel masking [1] and XML [6] for Logic BIST. The first two techniques suffer from limited observability since either only one scan chain output can be observed at a time (as in [4]) or all scan chains are together either blocked or observed at any scan shift cycle (as in [1]). Enhancements of both these techniques have been proposed to improve observability but at the expense of higher area overhead and/or larger control data [5].…”

Section: Introductionmentioning

confidence: 99%