Channel profile engineering for MOSFET's with 100 nm channel lengths

Jacobs, J.B.; Antoniadis, D.A.

doi:10.1109/16.381982

Cited by 49 publications

(9 citation statements)

References 14 publications

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“…In recent years, the physics and technology of sub-100 nm MOSFET devices have been the subject of numerous theoretical and experimental investigations [1][2][3][4]. The reported results indicate that the conventional MOSFET scaling becomes ineffective as the channel length falls below 100 nm.…”

Section: Introductionmentioning

confidence: 95%

Hot Carrier Reliability in Sub-0.1 μm nMOSFET Devices

Saha

1996

MRS Proc.

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This paper presents a systematic investigation of the hot-carrier effect in deep sub-micron silicon nMOSFET devices. A Hydrodynamic model for semiconductors was used to simulate the local carrier heating and the non-local transport phenomena in nMOSFETs of effective channel lengths 41, 66, 96, and 126 nrn under various biasing conditions. Test structures for device simulation were generated by using a super-steep retrograde channel profile with subsurface peak concentration of lx1018 cm-3 , and a gate oxide thickness of 3 nm. Superb MOSFET device characteristics were obtained for all devices. The simulation results show a significant decrease in substrate current, electron impact ionization rate, and peak electron temperature near the drain end of the channel with the decrease in supply voltage. The distribution of electrons into the substrate due to local electron heating is shown to be responsible for hot-carrier reliability in ultra-short channel silicon nMOSFET devices.

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Section: Introductionmentioning

confidence: 95%

Hot Carrier Reliability in Sub-0.1 μm nMOSFET Devices

Saha

1996

MRS Proc.

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“…However, the increase of channel doping concentration will degrade carrier mobility and raise threshold voltage (V T ) when drain-induced barrier lowering (DIBL) requirement is met [1]. Simulations of MOSFETs with retrograde doping [1]- [3] or ground plane (GP) [4], [5] showed that the retrograde doping or GP can help to mitigate SCEs and meanwhile achieve right V T values for small devices. The retrograde doping or GP in planar bulk MOSFETs is a heavily doped layer beneath the lightly or undoped channel layer, and it is usually continuous throughout the active region in the lateral direction.…”

Section: Introductionmentioning

confidence: 99%

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

Zhang

Zhu

et al. 2015

IEEE Trans. Electron Devices

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We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high-k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low V T . Compared with halo doping with the same V T,sat at V DD = 0.8 V, despite no I ON enhancement, the SPW reduces DIBL by 45% and enhances I EFF by 18%. Compared with halo doping with the same I OFF = 100 nA/µm at V DD = 0.8 V, the SPW structure reduces DIBL by 16%, enhances I ON by 5%, and improves I EFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT) Manuscript leakage in comparison with halo doping. Otherwise, 20 times larger BTBT leakage will emerge due to the profile overlap between retrograde doping and drain/extension doping.Index Terms-Band-to-band tunneling (BTBT), drain-induced barrier lowering (DIBL), ground plane (GP), halo, pocket, short-channel effect (SCE). tion.

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“…Channel engineering techniques such as retrograde well and halo implantation are introduced to improve scalability and performance of such devices ( Fig. 1(a)) [1,2]. However, the scalability of such a device structure is limited due to increased short channel effects [3].…”

Section: Introductionmentioning

confidence: 99%

Double-gate SOI devices for low-power and high-performance applications

Roy

Mahmoodi

Mukhopadhyay

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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Abstract:Double-Gate (DG) IntroductionThe scaling of conventional bulk CMOS technology is facing great challenges due to increased leakage and process variations with scaling down of device dimensions. Channel engineering techniques such as retrograde well and halo implantation are introduced to improve scalability and performance of such devices ( Fig. 1(a)) [1,2]. However, the scalability of such a device structure is limited due to increased short channel effects [3]. This has motivated the need for nonclassical silicon devices to extend CMOS scaling beyond 45nm node ( Fig. 1(b-d)). Ultra thin body SOI FETs employ very thin silicon body to achieve better control of the channel by the gate, and hence, reduced leakage and short channel effects. Use of intrinsic or lightly doped body reduces threshold voltage (Vt) variations due to random dopant fluctuations [4] and enhances the mobility of careers in the channel region and therefore ON current. In these devices, there can be a weak common back gate that is shared as a common substrate among all the transistors. Such a process is referred to as Ground Plane SOI (GP-SOI) [31]. Better scalability can be achieved by introduction of a second gate at the other side of the body of each transistor resulting in a Double Gate (DG) SOI structure ( Fig. 1(c)). Due to excellent control of short channel effects, double-gate SOI devices have emerged as the device of choice for circuit design in sub-50nm regime [5]. Low subthreshold leakage and higher ON current in DG devices make them suitable for circuit design in sub-50nm regime [6][7]. There are a variety of device structures suitable for double gate technologies. One of the promising structures is FinFET ( Fig. 1(d)) [8]. Double gate devices with isolated gates (independent gates) are also being developed [9][10]. Independent gate option can be useful for low power and mixed signal applications [10][11][12][13][14]. Such developments at the device level provide opportunities for new ways of circuit design for low power and high performance. In this paper, we first review the device design options for the double gate device structures (Section 2). Then, we discuss the circuit design options using such devices for logic and memory applications (Section 3 and 4). Double Gate SOI DevicesA classification of DG devices and their implications on circuit design is illustrated in Fig. 2. There are two main device processes possible for DG devices ( Fig. 2 and 3), namely (a) symmetric device with same gate material (e.g. near-midgap metals) and oxide thickness for the front and the back gate [15][16] and (b) asymmetric device with different strengths for front and back gates. Different strengths can be obtained by using either different oxide thickness (asymmetric oxide) [17] or materials of different work-function (e.g. n+ poly and p+ poly) for the front and the back gate (asymmetric work-function) [15].Regardless of the underlying device process, DG devices can also be classified in terms of their structure (Fig. 2). Typicall...

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Channel profile engineering for MOSFET's with 100 nm channel lengths

Cited by 49 publications

References 14 publications

Hot Carrier Reliability in Sub-0.1 μm nMOSFET Devices

Hot Carrier Reliability in Sub-0.1 μm nMOSFET Devices

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

Double-gate SOI devices for low-power and high-performance applications

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