Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

Abstract

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high-k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low V T . Compared with halo doping with the same V T,sat at V DD = 0.8 V, despite no I ON enhancement, the SPW reduces DIBL by 45% and enhances I EFF by 18%. Compared with halo doping with the same I OFF = 100 nA/µm at V DD = 0.8 V, the SPW structure reduces DIBL by 16%, enhances I ON by 5%, and improves I EFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT) Manuscript leakage in comparison with halo doping. Otherwise, 20 times larger BTBT leakage will emerge due to the profile overlap between retrograde doping and drain/extension doping.Index Terms-Band-to-band tunneling (BTBT), drain-induced barrier lowering (DIBL), ground plane (GP), halo, pocket, short-channel effect (SCE). tion.

Design approach to improve the performance of JAMFETs

“…This could generate a GC device without any implantation requirement of lightly doped region by chemical doping. The use of GC by chemical doping to improve the device performance has been a proven technique [24][25][26]. The improvement in device performance is measured in terms of I ON /I OFF ratio, sub-threshold slope (SS), drain-induced barrier lowering (DIBL), and cut-off frequency 'f T ' as shown in Figs.…”

Z‐shaped gate TFET with horizontal pocket for improvement of electrostatic behavior

“…21 The pocket layer insertion has been employed in conventional MOS devices to improve the SCEs significantly. 24,25 On the other hand, the introduction of pocket layer in the source or channel of a TFET leads to suppression of SCEs, reduction of SS, lower I OFF , and higher I ON, 21,22,[26][27][28][29] However, it is important to mention that controlled fabrication is one of the major issues in such pocket-based structures. In 2014, the experimental fabrication of a line TFET with 6 to 7-nm silicon pocket has been reported by Walke et al 16 In 2005, Jahan et al demonstrated the experimental feasibility of growing an ultrathin silicon layer up to 3.4 nm using the selective epitaxial growth process.…”

“…Kao et al, in 2012, proposed a solution to counter these limitations in gate on source configurations by introducing a pocket layer beneath the source 21 . The pocket layer insertion has been employed in conventional MOS devices to improve the SCEs significantly 24,25 . On the other hand, the introduction of pocket layer in the source or channel of a TFET leads to suppression of SCEs, reduction of SS, lower I OFF , and higher I ON, 21,22,26‐29 However, it is important to mention that controlled fabrication is one of the major issues in such pocket‐based structures.…”

A Novel Nanofabrication Technique of Silicon-Based Nanostructures

“…Silicon-based nanostructures including Si and SiO 2 are of great technological importance and considerable interest, and they have been extensively exploited for a wide variety of scientific and engineering applications ranging from attractive plasmonic [1, 2], sensitive biosensor devices [3, 4], phonics crystals to magnetic storage media [5, 6] and are also the building blocks for a broad range of nanoelectronic devices such as MOSFET [7, 8], nanofluidics [9, 10], and optoelectronics devices [11, 12]. Accordingly, there have been a large number of fabrication techniques and methods to produce highly controlled silicon-based nanostructures using top-down or bottom-up patterning strategies in the literatures [13–15].…”