Channel Thickness and Grain Size Engineering for Improvement of Variability and Performance in 3-D NAND Flash Memory

Nam, Kihoon; Park, Chanyang; Yoon, Jun-Sik; Yang, Giho; Park, Min Sang; Baek, Rock‐Hyun

doi:10.1109/ted.2022.3175681

Cited by 14 publications

(4 citation statements)

References 31 publications

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“…Figures 5(a Poly-Si semiconductor devices often have poorer performance compared to their monocrystalline silicon counterparts. [26][27][28][29] The main reason is the presence of grain boundaries and lattice defects in poly-Si, which restrict the movement of charge carriers. As a result, poly-Si devices tend to operate more slowly, consume more power, and exhibit greater variability in performance.…”

Section: Resultsmentioning

confidence: 99%

Advancements in single-crystal silicon with elevated-laser-liquid-phase-epitaxy (ELLPE) for monolithic 3D ICs

Shih,

Pan,

Chung

et al. 2024

Jpn. J. Appl. Phys.

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In this study, we present a low thermal budget Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) technique designed for the precise fabrication of single-crystal islands (SCIs) intended for use in middle-end-of-line (MEOL) FinFETs. Each of these single-crystal islands features a (100) orientation tended from Si seeding structure and is successfully integrated as channel materials in the MEOL circuit of a monolithic 3D integrated circuit (3DIC). This technique effectively mitigates the typical performance disparities associated with poly-Si channel materials in upper tiers, addressing a significant challenge in advanced electronic device fabrication and potentially enhancing the performance and reliability of MEOL FinFETs in monolithic 3DIC.

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Section: Resultsmentioning

confidence: 99%

Advancements in single-crystal silicon with elevated-laser-liquid-phase-epitaxy (ELLPE) for monolithic 3D ICs

Shih,

Pan,

Chung

et al. 2024

Jpn. J. Appl. Phys.

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“…Through the device fabrication process after MILC, the residual a-Si region was transformed into a high-resistance poly-Si region, 28) as shown in Fig. 5.…”

Section: S E 3 S H L Smentioning

confidence: 99%

Effects of crystallinity of silicon channels formed by two metal-induced lateral crystallization methods on the cell current distribution in NAND-type 3D flash memory

Matsuo,

Yamashita,

Shimada

et al. 2024

Jpn. J. Appl. Phys.

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Two metal-induced lateral crystallization (MILC) methods are proposed as candidate techniques to enhance cell current in future ultra-high-density NAND-type 3D flash memory devices. The channel crystallinity differs depending on the MILC method. In a single MILC, the channel is composed of single-crystal Si, whereas in a regional MILC, the channel comprises multiple crystal grains that are larger than those of the conventional polycrystalline Si. Using transmission electron microscopy, the inhibiting factor of MILC was modeled to reveal that the two MILC approaches result in different cell current distributions that are related to their degree of crystallinity. A comparison of these two cell current distributions in a 3D flash memory with over 900 word-line stacks showed that the single MILC delivers a higher median cell current with outliers on the lower side. In contrast, the regional MILC delivers a lower median cell current without outliers on the lower side.

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“…The edge of the target cell on the SL side was defined as X GB = 0. The 3-D random Voronoi grain pattern was applied under the remaining channel regions [33,34]. A U-shaped GB trap profile consisting of donor-like states and acceptor-like states was used for each GB [35].…”

Section: Threshold Voltage Shift By Poly-si Gbmentioning

confidence: 99%

Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory

An,

Yoon,

et al. 2023

Micromachines

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Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (IBL) and threshold voltage (VT). The VT shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔVT,CL) component and the poly-Si GB (ΔVT,GB) component. The extracted ΔVT,GB increases at higher TPGM due to the reduced GB potential barrier. Additionally, the ΔVT,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (XGB) and the bit line voltage (VBL).

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Channel Thickness and Grain Size Engineering for Improvement of Variability and Performance in 3-D NAND Flash Memory

Cited by 14 publications

References 31 publications

Advancements in single-crystal silicon with elevated-laser-liquid-phase-epitaxy (ELLPE) for monolithic 3D ICs

Advancements in single-crystal silicon with elevated-laser-liquid-phase-epitaxy (ELLPE) for monolithic 3D ICs

Effects of crystallinity of silicon channels formed by two metal-induced lateral crystallization methods on the cell current distribution in NAND-type 3D flash memory

Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory

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