2013
DOI: 10.1109/led.2013.2267809
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Channel Thickness Effect on High-Frequency Performance of Poly-Si Thin-Film Transistors

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Cited by 12 publications
(7 citation statements)
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“…The f T L and v eff values for flexible substrates and exfoliated MoS 2 values on a rigid substrate. Data taken from ref (right triangles) for MoS 2 FETs, ref (down triangle) for MoS 2 FETs, ref (up triangles) for MoS 2 FETs, ref (circle) for indium gallium zinc oxide (IGZO) TFTs, and ref (square) for polycrystalline silicon (poly-Si) TFTs. Reprinted with permission from ref .…”
Section: Mos2-based Flexible Fetsmentioning
confidence: 99%
“…The f T L and v eff values for flexible substrates and exfoliated MoS 2 values on a rigid substrate. Data taken from ref (right triangles) for MoS 2 FETs, ref (down triangle) for MoS 2 FETs, ref (up triangles) for MoS 2 FETs, ref (circle) for indium gallium zinc oxide (IGZO) TFTs, and ref (square) for polycrystalline silicon (poly-Si) TFTs. Reprinted with permission from ref .…”
Section: Mos2-based Flexible Fetsmentioning
confidence: 99%
“…Therefore, the parasitic gate capacitances also need to be considered for device design. Compared to the state-of-the-art RF planar TFTs ( f T = 17 GHz, SS ∼ 250 mV/decade), 9) better gate controllability and RF performances are obtained simultaneously in trigate devices. These results suggest the gate length of TFT can be scaled down further to get higher frequency response without suffering severe short channel effect by adopting the multi-gate structure.…”
Section: Trigate Tfts With Different S/d Extension Designsmentioning
confidence: 99%
“…In our previous conference report, 18) we have experimentally examined the dc and high-frequency characteristics of trigate poly-Si TFTs integrated in a 3D stackable circuit. Compared with the planar poly-Si TFTs, 9,19,20) our devices exhibit better gate controllability as well as higher cutoff frequency ( f T ). To further improve the high-frequency performance, we proposed a new channel layout, where the channel width increases gradually from the source side to the drain side.…”
Section: Introductionmentioning
confidence: 99%
“…In the past decades, several low-temperature crystallization methods, including solid-phase crystallization (SPC), [8][9][10] metal-induced crystallization (MIC) 11,12 and laser crystallization, 5,[13][14][15][16] have been proposed and performed on amorphous silicon (a-Si) layers via phase transition to a polycrystalline-state. SPC is usually executed by annealing the a-Si layer in a nitrogen ambient at a sufficiently low temperature (e.g., 600 o C) for a time-duration longer than 12 h. 8,9 The SPC process is a simple and mature technology without resorting to complex fabrication tools, but it takes a long duration of time for phase transition. Furthermore, the grain sizes of the SPC poly-Si layers are relatively small (typically less than 100 nm) and thus, channel mobility is to be improved.…”
mentioning
confidence: 99%
“…Furthermore, the grain sizes of the SPC poly-Si layers are relatively small (typically less than 100 nm) and thus, channel mobility is to be improved. SPC poly-Si TFTs with a channel thickness of 100 nm has been studied in a previous report, 9 showing remarkably high cut-off frequency (f T ) and maximum oscillation frequency (f max ) of 17 and 21 GHz, respectively, thanks to an aggressively shortened channel length (0.22 μm) in combination with self-aligned silicidation (SALICIDE) source/drain (S/D). 17 MIC was also proposed to facilitate the crystallization of a-Si at lower temperatures utilizing a metal (usually Ni) seeding layer.…”
mentioning
confidence: 99%