Chaos-Based Bitwise Dynamical Pseudorandom Number Generator On FPGA

García-Bosque, M.; Pérez-Resa, A.; Sánchez-Azqueta, Carlos; Aldea, C.; Celma, S.

doi:10.1109/tim.2018.2877859

Cited by 94 publications

(42 citation statements)

References 17 publications

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“…So, the modular operation is used to fix the upper range of state values. Two different modular recurrence relations are shown in Equations (1) and (2). It generates random number that is x i and y i in each iteration correspondingly.…”

Section: Concept Of Large Period Prbgmentioning

confidence: 99%

Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA

Gupta

Chauhan

2021

IET Computers & Digital Tech

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The authors present a new method for the generation of pseudorandom bits, based on coupled variable input linear congruential generator (LCG) and a clock divider. To prevent the system from falling into short-period orbits as well as increasing the randomness of the generated bit sequences, the proposed algorithm periodically changes the seed parameters of the LCG blocks. The proposed clock divider-based pseudorandom bit generator is compared with other LCG-based realisations, showing great improvement. First, a clock divider is utilised for generating a maximum length of 2 2n pseudorandom bits for n-bit operands size which leads to lowering the hardware cost. Secondly, it generates high-speed random bits at a uniform clock rate with one initial clock latency. Third, the proposed technique provides good statistical properties. The proposed architecture is implemented using Verilog HDL and further prototyped on commercially available field programmable gate array (FPGA) devices Virtex-5, Virtex-7, and Artix-7. The realisation of the proposed architecture in these FPGA devices accomplishes an improved data throughput and utilises minimum FPGA resources (in terms of look-up-tables and flip-flops) which are compared with the existing techniques. The generated bit sequence from the experiment is further analysed briefly for sequence size and verified for randomness by using the National Institute of Standards and Technology benchmark test.This is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.

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Section: Concept Of Large Period Prbgmentioning

confidence: 99%

Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA

Gupta

Chauhan

2021

IET Computers & Digital Tech

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“…This effect has been widely studied, and several solutions have been proposed [28,29]. Since (as explained in the Introduction) using a higher precision also implies using a much larger area to obtain the same throughput [21], a different approach was used in this work.…”

Section: Dynamics Degradation Due To Digitizationmentioning

confidence: 99%

A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology

et al. 2019

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In this work, a novel chaos-based stream cipher based on a skew tent map is proposed and implemented in a 0.18 μm CMOS (Complementary Metal-Oxide-Semiconductor) technology. The proposed ciphering algorithm uses a linear feedback shift register that perturbs the orbits generated by the skew tent map after each iteration. This way, the randomness of the generated sequences is considerably improved. The implemented stream cipher was capable of achieving encryption speeds of 1 Gbps by using an approximate area of ~ 20 , 000 2-NAND equivalent gates, with a power consumption of 24.1 mW. To test the security of the proposed cipher, the generated keystreams were subjected to National Institute of Standards and Technology (NIST) randomness tests, proving that they were undistinguishable from truly random sequences. Finally, other security aspects such as the key sensitivity, key space size, and security against reconstruction attacks were studied, proving that the stream cipher is secure.

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“…On the other hand, pseudo-random number generators (PRNGs) [ 4 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 ], and truly random number generators (TRNGs) [ 41 , 42 , 43 , 44 , 45 ] are important modules in the development of cryptosystems to be robust against different types of security attacks. Some of these PRNGs and TRNGs have been implemented in personal computers and in embedded systems [ 29 , 30 , 31 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 ].…”

Section: Introductionmentioning

confidence: 99%

“…Additionally, the method reported by [ 73 ] is used for the encryption of information using multiple-precision arithmetic [ 83 ]. The Python programming language [ 84 ] is used to process several significant decimals higher than that reported in the works [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 16 , 17 , 18 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 ] and which are based on the IEEE 754 standard [ 54 ], typically used in computers and FPGAs. It is important to emphasize that Python is a scientific programming language [ 84 ] with the following advantages: open-source, free license, an...…”

Section: Introductionmentioning

confidence: 99%

Implementing a Chaotic Cryptosystem by Performing Parallel Computing on Embedded Systems with Multiprocessors

Flores-Vergara

Inzunza-González²,

García-Guerrero³

et al. 2019

Entropy

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Profiling and parallel computing techniques in a cluster of six embedded systems with multiprocessors are introduced herein to implement a chaotic cryptosystem for digital color images. The proposed encryption method is based on stream encryption using a pseudo-random number generator with high-precision arithmetic and data processing in parallel with collective communication. The profiling and parallel computing techniques allow discovery of the optimal number of processors that are necessary to improve the efficiency of the cryptosystem. That is, the processing speed improves the time for generating chaotic sequences and execution of the encryption algorithm. In addition, the high numerical precision reduces the digital degradation in a chaotic system and increases the security levels of the cryptosystem. The security analysis confirms that the proposed cryptosystem is secure and robust against different attacks that have been widely reported in the literature. Accordingly, we highlight that the proposed encryption method is potentially feasible to be implemented in practical applications, such as modern telecommunication devices employing multiprocessors, e.g., smart phones, tablets, and in any embedded system with multi-core hardware.

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Chaos-Based Bitwise Dynamical Pseudorandom Number Generator On FPGA

Cited by 94 publications

References 17 publications

Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA

Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA

A 1 Gbps Chaos-Based Stream Cipher Implemented in 0.18 μm CMOS Technology

Implementing a Chaotic Cryptosystem by Performing Parallel Computing on Embedded Systems with Multiprocessors

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