1984
DOI: 10.1049/el:19840643
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Characteristics of GaAs/AlGaAs MODFETs grown directly on (100) silicon

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Cited by 81 publications
(7 citation statements)
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“…Other results of GaAs layers directly on Si [3] and GaAsiAlGaAs MODFET's with extremely high transconductance (175 mS/mm at 300 K and 275 mS/mm at 77K) and with low field 10 K mobilities of 51 000 cm2/V. s were also reported [4]. Very recently, GaAs MESFET's directly on Si substrates with transconductances of about 85 mS/mm [5] which are inferior to those prepared on GaAs substrates were reported.…”
Section: Ue To the Possibilities It Offers Such As Integration Ofmentioning
confidence: 84%
“…Other results of GaAs layers directly on Si [3] and GaAsiAlGaAs MODFET's with extremely high transconductance (175 mS/mm at 300 K and 275 mS/mm at 77K) and with low field 10 K mobilities of 51 000 cm2/V. s were also reported [4]. Very recently, GaAs MESFET's directly on Si substrates with transconductances of about 85 mS/mm [5] which are inferior to those prepared on GaAs substrates were reported.…”
Section: Ue To the Possibilities It Offers Such As Integration Ofmentioning
confidence: 84%
“…50) In 1984, Fischer et al employed a GaAs=GaAlAs superlattice to reduce the dislocation density in GaAs heteroepitaxially grown on a silicon substrate. 51) Umeno's group grew GaAs of good quality on a silicon substrate with an AlP, AlGaP, GaP=GaAs 0.5 P 0.5 , superlattice and a GaAs 0.5 P 0.5 =GaAs superlattice. 52) In their case, the superlattice consisted of layers with different lattice constants, which induced a strain in the layers.…”
Section: Utilization Of a Superlatticementioning
confidence: 99%
“…Heterogeneous integration of compound semiconductor devices onto Si CMOS offers the promise of integrated circuits (IC's) with enhanced performance as well as microsystems with new functions beyond CMOS. Despite large mismatches in lattice constant and coefficient of thermal expansion (1), a variety of III-V compound semiconductors have been epitaxially deposited directly on the Si substrate by incorporating buffer layers that control dislocations in the active device layers (2)(3)(4)(5). This allows for mixed integration III-V devices on the same level as the Si CMOS transistors.…”
Section: Introductionmentioning
confidence: 99%