Characteristics of impact-ionization current in the advanced self-aligned polysilicon-emitter bipolar transistor

Liu, T.M.; Chiu, T.-Y.; Archer, V.D.; Kim, H.H.

doi:10.1109/16.119024

Cited by 29 publications

(1 citation statement)

References 16 publications

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“…When npn HBTs are biased in the active region at high V CB , electron-hole pairs are generated in the base-collector (BC) space charge region by impact ionization. The generated electrons are swept into the collector, contributing a positive term to the collector current I C , while the generated holes are injected into the base contributing a negative term to the base current I B , which increases on increasing V CB [12,15]. Impact ionization effects can be quantitatively evaluated by measuring the multiplication factor M − 1 defined as the ratio of generated electron-hole pairs to the number of carriers injected in the collector.…”

Section: Hot Electron Effects and Impact Ionizationmentioning

confidence: 99%

Untitled

Carlo¹,

Lugli²,

Canali³

et al. 1998

Semicond. Sci. Technol.

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We present a detailed investigation of light emission phenomena connected with the presence of hot carriers in AlGaAs/GaAs heterojunction bipolar transistors. Electrons heated by the strong electric field at the base-collector junction lead to both impact ionization and light emission. A new general-purpose weighted Monte Carlo procedure has been developed to study such effects. The measured hot electroluminescence is attributed to radiative recombinations within the valence and the conduction bands. Good agreement is found between theory and experiment.

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Section: Hot Electron Effects and Impact Ionizationmentioning

confidence: 99%

Untitled

Carlo¹,

Lugli²,

Canali³

et al. 1998

Semicond. Sci. Technol.

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Hot Electron Induced Impact Ionization and Light Emission in GaAs Based MESFETs, HEMTs, PM-HEMTs and HBTs

Canali

Tedesco

Zanoni

et al. 1993

Negative Differential Resistance and Instabilities in 2-D Semiconductors

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BiCMOS Process Technology

Eklund

Haken

Havemann

et al. 1993

BiCMOS Technology and Applications

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IntroductionFor high performance LSI and VLSI digital ciIcuit applications, BiCMOS technology has become predominantly driven from a CMOS processing base. The principle reason for this is that LSI and VLSI digital BiCMOS ciIcuits tend to be CMOS-intensive because of power dissipation limitations (for example, high density ECL I/O SRAMs and gate arrays). The CMOS-intensive nature of these ciIcuits requires a process technology that will result in the highest possible CMOS performance. Consequently, BiCMOS fabrication technology tends to be CMOSbased, and the process steps needed to realize a high performance bipolar device are usually merged with a core CMOS process flow [3.1, 3.2, 3.3]. In the case of analog BiCMOS, the increasing demand to have on-board digital logic integration has also resulted in these processes being CMOS-oriented.As CMOS technology has been extended to cross the "I jJJD discontinuity" into the submicron regime, the structural requirements for realizing high performance CMOS and bipolar transistors have tended to converge. For example, it is common practice in submicron CMOS processes to incorporate silicided gates and diffusions to achieve lower sheet resistance (from typically 20-50 ohms/sq to 1.5 ohms/sq). Figure 3.1 shows how the same silicidation technology can be used to simultaneously enhance the performance of both CMOS devices and polysilicon emitter bipolar transistors. For the bipolar device, the silicidation process can be used to minimize the emitter resistance by cladding the polysilicon in a similar manner as is done for the CMOS gates. It can also be used to decrease the extrinsic base resistance by cladding the P+ diffusion, again as is done for the PMOS source/drains.Many other process steps in a submicron CMOS and bipolar process can be merged and shared to realize a high performance BiCMOS technology with the minimum of added complexity, compared to a core CMOS process flow. One example of how a key process feature of one device can be advantageously shared with the other is the case of a buried N+ layer. Buried N+ layers are common features in bipolar processes and are introduced to minimize collector resistance. However, the buried layer can also be utilized in CMOS ciIcuits to reduce latchup susceptibility if it is placed underneath the N-wells containing PMOS devices, as shown in Fig. 3.1. This results in the ultimate "retrograde" CMOS well proftle and eliminates the need for epitaxial starting material, which is often used in submicron CMOS to prevent latchup [3.4, 3.5].

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Characteristics of impact-ionization current in the advanced self-aligned polysilicon-emitter bipolar transistor

Cited by 29 publications

References 16 publications

Untitled

Untitled

Hot Electron Induced Impact Ionization and Light Emission in GaAs Based MESFETs, HEMTs, PM-HEMTs and HBTs

BiCMOS Process Technology

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