Characterization &amp; modeling of low electric field gate-induced-drain-leakage [MOSFET]

Rideau, D.; Dray, A.; Gilibert, Fabien; Agut, Francois; Giguerre, L.; Gouget, Gilles; Minondo, M.; Juge, André

doi:10.1109/icmts.2004.1309469

Cited by 15 publications

(5 citation statements)

References 15 publications

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“…The off-current at higher positive gate voltage is strongly limited by the large gate-induced drain leakage (GIDL) due to the smaller band gap of Si 0.5 Ge 0.5 and therefore easier tunneling activation. [12,13] The minimum sub-threshold slope (SS) of the device is about 100 mV/dec, which is much improved compared with a similar device reported previously. [14] The sub-threshold slope is larger than that of conventional Si transistors due to the nonsurface channel structure.…”

mentioning

confidence: 62%

Electrical Characteristics of High Mobility Si/Si _0.5 Ge _0.5 /SOI Quantum-Well p-MOSFETs with a Gate Length of 100 nm and an Equivalent Oxide Thickness of 1.1 nm

Mu¹,

Yu²,

Zhang³

et al. 2013

Chinese Phys. Lett.

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Short-channel high-mobility Si/Si0.5Ge0.5/silicon-on-insulator (SOI) quantum-well p-type metal-oxide-semiconductor field effect transistors (p-MOSFETs) were fabricated and electrically characterized. The transistors show good transfer and output characteristics with 𝐼on/𝐼 off ratio up to 10 5 and sub-threshold slope down to 100 mV/dec. HfO2/TiN gate stack is employed and the equivalent oxide thickness of 1.1 nm is achieved. The effective hole mobility of the transistors reaches 200 cm 2 /V•s, which is 2.12 times the Si universal hole mobility.

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mentioning

confidence: 62%

Electrical Characteristics of High Mobility Si/Si _0.5 Ge _0.5 /SOI Quantum-Well p-MOSFETs with a Gate Length of 100 nm and an Equivalent Oxide Thickness of 1.1 nm

Mu¹,

Yu²,

Zhang³

et al. 2013

Chinese Phys. Lett.

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“…The temperature dependence of the leakage is shown in Figure 7 (b). At low drain bias the leakage is dependent on temperature with very little drain bias/ electric field dependence, suggesting that the leakage is dominated by trap assisted tunneling (14). This is not surprising as these structures have a nonoptimized gate oxide process with a high density of interface traps, D it , 3 x 10 11 cm -2 .…”

Section: Off-state Leakagementioning

confidence: 98%

Influence of Strained Si_1-yGe_y Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0

2006

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Hole mobility enhancements of 5 to 8X are demonstrated in heterostructure p-MOSFETs for strained Si1-yGey fractions, y ranging from 0.8 to 1. The influence of SiGe film thickness on hole mobility for strained Si0.3Ge0.7-channel p-MOSFETs is also investigated. Mobility is found to decrease significantly for channel thicknesses below 7 nm. Off-state leakage increases exponentially with increasing Ge concentration in the channel. Temperature dependent measurements of the leakage are consistent with trap-assisted tunneling at low drain-to-gate bias, and with band-to-band tunneling at higher biases. A reduction in leakage is observed for SiGe channel layer thicknesses below 7 nm. The results presented in this work are relevant to modeling and optimization of the performance of high mobility, high Ge concentration strained heterostructure p-MOSFETS.

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“…Another important point interesting to evaluate in a NOR-architecture memory array is the BitLine Leakage (BLL), due to the Gate Induced Drain Leakage (GIDL) current in Band-to-Band Tunneling (BBT) regime, during the CHE programming operation [15]. As highlighted in previous studies [16][17][18], several technological parameters, such as cell LDD doping (dose, tilt, and energy), drain-gate overlap, or STI shape have an impact on electric fields in the drain-bulk junction, responsible for GIDL.…”

Section: Bitline Leakage Optimizationmentioning

confidence: 99%

Push the flash floating gate memories toward the future low energy application

Marca¹,

Just²,

Régnier³

et al. 2013

Solid-State Electronics

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In this paper the consumption of Flash Floating Gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances and reliability. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

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Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET]

Cited by 15 publications

References 15 publications

Electrical Characteristics of High Mobility Si/Si _0.5 Ge _0.5 /SOI Quantum-Well p-MOSFETs with a Gate Length of 100 nm and an Equivalent Oxide Thickness of 1.1 nm

Electrical Characteristics of High Mobility Si/Si _0.5 Ge _0.5 /SOI Quantum-Well p-MOSFETs with a Gate Length of 100 nm and an Equivalent Oxide Thickness of 1.1 nm

Influence of Strained Si_1-yGe_y Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0

Push the flash floating gate memories toward the future low energy application

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Characterization & modeling of low electric field gate-induced-drain-leakage [MOSFET]

Cited by 15 publications

References 15 publications

Electrical Characteristics of High Mobility Si/Si 0.5 Ge 0.5 /SOI Quantum-Well p-MOSFETs with a Gate Length of 100 nm and an Equivalent Oxide Thickness of 1.1 nm

Electrical Characteristics of High Mobility Si/Si 0.5 Ge 0.5 /SOI Quantum-Well p-MOSFETs with a Gate Length of 100 nm and an Equivalent Oxide Thickness of 1.1 nm

Influence of Strained Si1-yGey Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0

Push the flash floating gate memories toward the future low energy application

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Electrical Characteristics of High Mobility Si/Si _0.5 Ge _0.5 /SOI Quantum-Well p-MOSFETs with a Gate Length of 100 nm and an Equivalent Oxide Thickness of 1.1 nm

Electrical Characteristics of High Mobility Si/Si _0.5 Ge _0.5 /SOI Quantum-Well p-MOSFETs with a Gate Length of 100 nm and an Equivalent Oxide Thickness of 1.1 nm

Influence of Strained Si_1-yGe_y Layer Thickness and Composition on Hole Mobility Enhancement in Heterostructure p-MOSFETs with Ge Contents y from 0.7 to 1.0