Characterization and Modeling of Self-Heating in Nanometer Bulk-CMOS at Cryogenic Temperatures

Abstract

This work presents a self-heating study of a 40nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel and in the surrounding silicon substrate, using the gate resistance and silicon diodes as sensors, respectively. Since self-heating depends on factors such as device geometry and power density, the test structure characterized in this work was specifically designed to resemble actual devices used in cryogenic qubit control ICs. Severe self-heating was observed at deep-cryogenic ambient temperatures, resulting in a channel temperature rise exceeding 50 K and having an impact detectable at a distance of up to 30 µm from the device. By extracting the thermal resistance from measured data at different temperatures, it was shown that a simple model is able to accurately predict channel temperatures over the full ambient temperature range from deep-cryogenic to room temperature. The results and modeling presented in this work contribute towards the full selfheating-aware IC design-flow required for the reliable design and operation of cryo-CMOS circuits.

Modelling of self-heating effect in FDSOI and bulk MOSFETs operated in deep cryogenic conditions

“…5 shows that the self-heating temperature rise model of Eq. ( 7) reproduces reasonably well the ∆T(P,T) data of [6] for 40nm bulk MOSFETs operated at deep cryogenic temperatures.…”

“…CMOS devices recently reported by Hart et al [6] and shown in Fig 5 (red solid lines). They found that the differential thermal resistance deduced from ∆T(P,T) data can also be fitted by an equation of the form, * = ) ,…”

“…This self-heating effect (SHE) can in turn severely affect the device performance, by reducing the carrier mobility, shifting the threshold voltage [1] or degrading the device reliability [2,3], with implications in circuits operation [4]. The thermal effects play a more fundamental role in cryogenic electronics as the temperature increase due to SHE can be of the same order or even higher than the ambient temperature in FDSOI [5] and even in bulk MOSFETs [6]. Furthermore, at very low temperature (well below 1K), the cooling power drops down drastically (typically, 1W at 1K, 1mW at 100mK), such that the thermal management becomes more drastic.…”

Cryogenic CMOS for Qubit Control and Readout

“…13), showing intermodulation products <-30dBc, sufficient for a 99.99% readout fidelity [39]. The measured receiver noise temperature is 44K, which we believe might be limited by device self-heating [42]. Analysis of readout fidelity based on receiver noise figure and other parameters can be found in [39].…”

“…In both cases, electromagnetic and thermal crosstalk from the electronics must be tightly controlled not to spoil qubit performance. For instance, cryogenic self-heating from CMOS transistors can significantly affect the temperature of on-chip devices even at tens of μm distance [42], thus potentially limiting the integration density of such a quantum/classical system. As sketched above, the path towards the integration of the cryogenic electronic interface to support large-scale quantum processors will still require significant innovations.…”