Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack

Brocard, M.; Maître, Patrick Le; Bermond, C.; Bar, P.; Anciant, R.; Farcy, A.; Lacrevaz, T.; Leduc, P.; Coudrain, P.; Hotellier, N.; Jamaa, Haykel Ben; Chéramy, S.; Sillon, N.; Marin, J. C.; Flechet, B.

doi:10.1109/ectc.2012.6248903

Cited by 11 publications

(5 citation statements)

References 11 publications

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“…3(c). The TSVs being investigated of GSG-and GS-mode is and in diameter, respectively [14], [15]. Note that the proposed models accord well with the measurements, which also verify the good applicability of our proposed model.…”

Section: Results and Validationsupporting

confidence: 75%

“…As shown in Fig. 1, the ground bounce and power rail collapse voltages can be determined by the circuit equations as (12) (13) where ; The total voltage drop around the current loop, formed by the signal TSV and the right side ground TSV, is the product of the loop inductance of this current loop and the time derivative of the current, calculated as (14) The loop inductance of GSG-type TSVs with frequency loss in high frequency circuits [11] can then be acquired as (15) where is the operating frequency;…”

Section: B Electrical Model Of Loop Inductance Of Gsg-type Tsv Pairmentioning

confidence: 99%

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Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

Liu

Zhu

Yang

et al. 2015

IEEE Microw. Wireless Compon. Lett.

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In this letter, the parasitic inductance of tapered ground-signal-ground (GSG) type through-silicon via (TSV) pair used in high speed three-dimensional integrated circuits (3-D ICs) are proposed. Rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs. The proposed models are in good agreement with the 3-D electromagnetic (EM) simulator and measurement results with maximum errors of 8%.Index Terms-Ground-signal-ground (GSG), high speed threedimensional (3D) integrated circuit (IC), inductance modeling, tapered through-silicon vias (TSVs).

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Section: Results and Validationsupporting

confidence: 75%

Section: B Electrical Model Of Loop Inductance Of Gsg-type Tsv Pairmentioning

confidence: 99%

Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

Liu

Zhu

Yang

et al. 2015

IEEE Microw. Wireless Compon. Lett.

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show abstract

“…Moreover, the interconnection configuration can achieve higher density integration of microwave application in the complicated 3D package modules. Accordance with the recent references [4][5][6] , some preliminary work on the performance of the single TSV in high frequency range have been reported. However, the aspect ratios (AR) of the TSVs fabricated in these papers are relatively low (AR=1-3).…”

Section: Introductionsupporting

confidence: 74%

A novel wafer-level double side packaging and its high frequency performance

Xiao

Tang

et al. 2013

2013 IEEE International Conference on Industrial Technology (ICIT)

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In this paper, a wafer-level System-in-Packaging structure using through silicon via (TSV) for integration on both sides of the silicon wafer is presented. It is composed of BCB/ metal multilayers, high-resistivity silicon substrate with TSV. To reduce the transmission loss in microwave frequency, not only the high-resistivity silicon is used, but also a special TSV structure with 6 grounded shielding vias around the core via are adopted. Microstrip line (MSL) is used to transmit highfrequency signal on package plane together with the low permittivity intermediate dielectric polymer, BCB. Descriptions on the interconnection structure and the fabrication process are included. The microwave measurement result of the MSL connected by TSVs is measured up to 35GHz. The results of both the simulation and the measurement are presented.

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“…The TSV characteristics are the following: a 10µm diameter, an 80µm depth (aspect ratio 1/8). An accurate spice RF model of the TSV can be found in [11].…”

Section: B Spice Simulation Resultsmentioning

confidence: 99%

A 3D IC BIST for pre-bond test of TSVs using ring oscillators

Fkih¹,

Vivet²,

Rouzeyre

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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Abstract-3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues, especially for TSVs. In this paper we propose a novel Built-In-Self-Test (BIST) architecture for pre-bond testing of TSVs in 3D stacked integrated circuits. The main idea is to measure the variation of TSVs capacitances in order to detect defective TSVs. The BIST architecture is based on ring oscillators, frequencies of which depend on TSVs capacitances. The proposed BIST is integrated within the JTAG standard. This paper presents spice simulation results and logic synthesis results of the proposed TSV ring oscillator structure using a 65 nm CMOS technology, including 10 µm diameter TSV middle technology. Due to local process variations, the proposed test architecture is limited in accuracy; it detects only large capacitive faults on TSVs.

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Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack

Cited by 11 publications

References 11 publications

Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

A novel wafer-level double side packaging and its high frequency performance

A 3D IC BIST for pre-bond test of TSVs using ring oscillators

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