Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

Abstract

In this letter, the parasitic inductance of tapered ground-signal-ground (GSG) type through-silicon via (TSV) pair used in high speed three-dimensional integrated circuits (3-D ICs) are proposed. Rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs. The proposed models are in good agreement with the 3-D electromagnetic (EM) simulator and measurement results with maximum errors of 8%.Index Terms-Ground-signal-ground (GSG), high speed threedimensional (3D) integrated circuit (IC), inductance modeling, tapered through-silicon vias (TSVs).

Electrical models of through silicon Vias and silicon‐based devices for millimeter‐wave application

“…The parasitic inductance of tapered GSG-TSV structure for high speed 3D ICs were proposed in. 10 The 3-D view of tapered TSV is shown in Figure 2B. Moreover, rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs.…”

“…Due to the better shielding effect of ground TSVs, the Ground‐Signal‐Ground (GSG) type TSVs were designed to achieve mmW applications in 3D ICs, as shown by Figure . Rigorous closed‐form formulas of the inductance, exploiting loop and partial inductances, were derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS‐mode TSVs. Air‐gap was exploited as the insulation layer in, due to the low permittivity.…”

“…The through‐silicon vias (TSVs) are short vertical interconnections that carry a variety of signals (power, clock, and data) between different layers within three‐dimensional integrated circuits (3D ICs), which can significantly shorten the interconnect length between circuit blocks and thereby reduces the time delay and power consumption . Correspondingly, the TSV‐based 3D ICs provide opportunities for the reduction of dimensions and power consumption, which is an exciting technology due to the smaller form factor, improved global signaling, and ability to integrate heterogeneous circuits within a single platform.…”

“…On the other hand, the electrical characteristics of TSVs are critical to the performance of mmW 3D ICs due to the abundant utilization of TSVs. Therefore, many studies have been carried out for modeling of TSV interconnects together with their fabrication technologies . What is more, TSVs exploiting new structures and materials were also researched to enhance the performance of 3D ICs …”

Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)

“…The electrical model in terms of parasitic resistance, capacitance and inductance are important because the circuit overall performances can be estimated by combing models. There are already many models (tapered, cylindrical, annular, and coaxial TSVs) have been proposed to model the TSV electrical characterization [6,7,8,9,10,11], however, most of the models did not consider the effect of temperature. Owing to the increasing integration density, a large amount of heat is generated during operating.…”