Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs

Tewksbury, T.; Lee, Hae-Seung

doi:10.1109/4.278345

Cited by 78 publications

(18 citation statements)

References 37 publications

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“…The recovery time depends on the energylevel of the stress-induced traps and their separation from the interface. [45][46][47][48] The faster recovery time of the AZ sample may be due to the fact that the stress-induced traps are located near the interface. 49 In order to keep the AZ sample with good electrical quality and also more robust to bias stressing, the Al gate electrode can first undergo an ultraviolet ozone annealing for 15 min to form a dense layer of Al 2 O 3 on top of the Al gate electrode before the ZrO 2 deposition.…”

Section: Resultsmentioning

confidence: 98%

Comparison of CuPc-based organic thin-film transistors made by different dielectric structures

Tang

Greiner

et al. 2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Copper phthalocyanine-based organic thin-film transistors (OTFTs) with gate dielectric made by different combinations of ZrO2 and Al2O3 are fabricated. Experimental results show that as compared to the OTFTs with ZrO2/Al2O3 stacked and Al2O3/ZrO2/Al2O3 sandwiched gate dielectric, the device fabricated with the Al2O3/ZrO2 stacked gate dielectric manifests better electrical properties such as larger on/off ratio, smaller subthreshold slope, and higher carrier mobility. This could be explained by the fact that Al2O3 has good interface properties with CuPc and can act as a barrier layer, which prevents intermixing of materials at the organic/insulator interface and can slow oxygen diffusion through Al-O matrix, thus suppressing interfacial trap density. The gate-bias stress effect on the performance of OTFTs is also investigated. It is found that the threshold voltage shifts toward positive direction with stress time under a negative gate bias voltage. Longer stress times cause more degradation of the subthreshold and on/off ratio, probably due to more defect-state creation in the channel and an increase of interfacial traps and oxide charges in the dielectric during stress. Results also indicate that OTFTs with Al2O3 interlayer between the high-k dielectric and the gate electrode have less degradation in subthreshold and on/off ratio after a 3600-s stress. The involved mechanism lies in that the Al2O3 interlayer at the high-k dielectric/gate electrode interface can effectively block the injection of electrons from the gate electrode into the high-k material during electrical stress and thus less stress-induced interfacial traps and negative oxide charges in the devices. The electrical characteristics of the OTFTs after the removal of gate bias for a period of time are also studied.

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Section: Resultsmentioning

confidence: 98%

Comparison of CuPc-based organic thin-film transistors made by different dielectric structures

Tang

Greiner

et al. 2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…The threshold voltage shift is observed to decrease slightly with increasing gate length. This can be explained as an edge effect, due to higher trap densities around the periphery of the gate oxide arising from damage created during implantation of the source-drain regions or plasma etching process [14]. Fig.…”

Section: Resultsmentioning

confidence: 99%

Threshold voltage shift of submicron p-channel MOSFET due to Si surface damage from plasma etching process

et al. 2007

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“…As concrete example for this relationship we use a current source in a current steering DA converter. The DAC specifications for resolution and yield determine the tolerable current variation σ (I ) I of the current sources (van den Bosch et al, 2001). These matching requirements can be converted into area requirements:…”

Section: Benefits In Speed-accuracy-power Trade-offmentioning

confidence: 99%

“…Measured V T shifts reach values in the range of 100 mV, while values around 10 mV are supposed to be tolerable for digital circuits. Time constants are reported from µs up to ms. For circuit simulations, an equivalent circuit model can be used (Fulde et al, 2006;Tewksbury and Lee, 1994) as shown in Fig. 9.…”

Section: Charge Trapping -Modeling and Impact On Analog Circuitsmentioning

confidence: 99%

Analog circuits using FinFETs: benefits in speed-accuracy-power trade-off and simulation of parasitic effects

Fulde¹,

Engelstädter

Knoblinger

et al. 2007

Adv. Radio Sci.

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Abstract. Multi-gate FET, e.g. FinFET devices are the most promising contenders to replace bulk FETs in sub-45 nm CMOS technologies due to their improved sub threshold and short channel behavior, associated with low leakage currents. The introduction of novel gate stack materials (e.g. metal gate, high-k dielectric) and modified device architectures (e.g. fully depleted, undoped fins) affect the analog device properties significantly. First measurements indicate enhanced intrinsic gain (gm/gDS) and promising matching behavior of FinFETs. The resulting benefits regarding the speed-accuracy-power trade-off in analog circuit design will be shown in this work. Additionally novel device specific effects will be discussed. The hysteresis effect caused by charge trapping in high-k dielectrics or self-heating due to the high thermal resistor of the BOX isolation are possible challenges for analog design in these emerging technologies. To gain an early assessment of the impact of such parasitic effects SPICE based models are derived and applied in analog building blocks.

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Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs

Cited by 78 publications

References 37 publications

Comparison of CuPc-based organic thin-film transistors made by different dielectric structures

Comparison of CuPc-based organic thin-film transistors made by different dielectric structures

Threshold voltage shift of submicron p-channel MOSFET due to Si surface damage from plasma etching process

Analog circuits using FinFETs: benefits in speed-accuracy-power trade-off and simulation of parasitic effects

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