Characterization of 8T SRAM cells using 16 nm FinFET technology

Monica, Menendez; Chandramohan, P

doi:10.1109/icspcom.2016.7980614

Cited by 9 publications

(5 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…(SRAM) designs. A lot of effort has been put forth to research and design FinFET SRAM cells [17], [18], [19], [20]. However, one could argue that a full SRAM IC could not be implemented without the use of a FinFET CP.…”

Section: Finfet Vs Traditional Cmosmentioning

confidence: 99%

A Low Power FinFET Charge Pump for Energy Harvesting Applications

Whittaker

Rizkalla

Ytterdal

2020

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)

View full text Add to dashboard Cite

Section: Finfet Vs Traditional Cmosmentioning

confidence: 99%

A Low Power FinFET Charge Pump for Energy Harvesting Applications

Whittaker

Rizkalla

Ytterdal

2020

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)

View full text Add to dashboard Cite

“…From Figure 6(a), the SNM of the 6T SRAM cell is 400mV. The value is better than the others work [5], [7], [8]. It verifies that FinFET based 6T SRAM has higher ability to retain stable data during standby mode operation.…”

Section: B Static Noise Margin (Snm) Of 22nm Finfet Based 6t Srammentioning

confidence: 74%

“…However, the 6T SRAM cell scheme faces the degradation of performance during the read operation. Therefore, another topology of 8T SRAM cell is proposed to solve the destructive read problem that occurs in the conventional 6T SRAM cell by separating the read and write operation [5][6][7][8]. The storage nodes of the 6T SRAM cell are used to store the logical values '0' and '1'.…”

Section: Introductionmentioning

confidence: 99%

Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

Alias¹,

Hamzah²,

Tan³

et al. 2019

EECSI

View full text Add to dashboard Cite

The development of the nanotechnology leads to the shrinking of the size of the transistors to nanometer region. However, there are a lot of challenges due to size scaling of the transistors such as short channel effects (SCEs) and threshold voltage roll-off issues. Fin-Type Field Effect Transistor (FinFET) is another alternative technology to solve the issues of the conventional MOSFET and increase the performance of the Static Random Access Memory (SRAM) circuit design. FinFET based SRAMs are faster and more reliable which are often used as memory cache for high speed operation. However, 6T SRAM cell suffers from access transistor sizing conflict resulting in a trade-off between read and write stability. This paper presents an investigation of the stability performance in retention, read and write mode of 22nm FinFET based 8T SRAM cell. The performance comparison of 22nm FinFET based 6T and 8T SRAMs were made. The simulation of the SRAM model are carried out in GTS Framework TCAD tool based on 22nm technology. In 8T SRAM cell, two n-FinFETs are added to the conventional 6T SRAM cell which will be controlled by the Read Word Line (RWL) to isolate the read and write operation path for better read stability. FinFET based 8T SRAM cell gives better performance in Static Noise Margin (SNM) and power consumption than 6T SRAM cells. The simulation results affirms the proposed FinFET based 8T SRAM improved read static noise margin by 166.67% and power consumption by 76.13% as compared to the FinFET based 6T SRAM.

show abstract

“…The proposed novel FinFET and CNFET SRAMs are compared with the conventional FinFET 8T SRAM [21,22]. All FinFETs and CNFETs used in the experiment were simulated at room temperature (27 • C) and VDD = 0.9 v in 32-nm technology.…”

Section: Sram Operationmentioning

confidence: 99%

“…The traditional 8T FinFET data are a result of re-simulating the traditional 8T SRAM structure [21,22] under the same conditions as our proposed 8T SRAM. The total memory power consumption and delay may vary depending on type of the applied AI chip and CNN model.…”

Section: Performance Analysismentioning

confidence: 99%

Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles

et al. 2021

View full text Add to dashboard Cite

Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate and can provide high throughput. However, these SRAMs have problems that they consume high power and occupy a large area to accommodate complex AI models. A carbon nanotube field-effect transistors (CNFET) device has been reported as a potential candidates for AI devices requiring ultra-low power and high-throughput due to their satisfactory carrier mobility and symmetrical, good subthreshold electrical performance. Based on the CNFET and FinFET device’s electrical performance, we propose novel ultra-low power and high-throughput 8T SRAMs to circumvent the power and the throughput issues in Artificial Intelligent (AI) computation for autonomous vehicles. We propose two types of novel 8T SRAMs, P-Latch N-Access (PLNA) 8T SRAM structure and single-ended (SE) 8T SRAM structure, and compare the performance with existing state-of-the-art 8T SRAM architectures in terms of power consumption and speed. In the SRAM circuits of the FinFET and CNFET, higher tube and fin numbers lead to higher operating speed. However, the large number of tubes and fins can lead to larger area and more power consumption. Therefore, we optimize the area by reducing the number of tubes and fins without compromising the memory circuit speed and power. Most importantly, the decoupled reading and writing of our new SRAMs cell offers better low-power operation due to the stacking of device in the reading part, as well as achieving better readability and writability, while offering read Static Noise Margin (SNM) free because of isolated reading path, writing path, and greater pull up ratio. In addition, the proposed 8T SRAMs show even better performance in delay and power when we combine them with the collaborated voltage sense amplifier and independent read component. The proposed PLNA 8T SRAM can save 96%, while the proposed SE 8T SRAM saves around 99% in writing power consumption compared with the existing state-of-the-art 8T SRAM in FinFET model, as well as 99% for writing operation in CNFET model.

show abstract

Characterization of 8T SRAM cells using 16 nm FinFET technology

Cited by 9 publications

References 11 publications

A Low Power FinFET Charge Pump for Energy Harvesting Applications

A Low Power FinFET Charge Pump for Energy Harvesting Applications

Low-Power And High Performance Of An Optimized FinFET Based 8T SRAM Cell Design

Ultra-Low Power and High-Throughput SRAM Design to Enhance AI Computing Ability in Autonomous Vehicles

Contact Info

Product

Resources

About