Characterization of a novel radiation hardened by design (RHD14) bit-cell based on 20-nm FinFET technology using TCAD simulations

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications

“…When HRLP16T cell stores value 0, i.e., Q = S1 = 0 and QB = S1 = 1, the Q, S0 and S1 are sensitive nodes. Similarly, When HRLP16T cell stores value 1, i.e., Q = S1 = 1 and QB = S1 = 0, the QB, S0 and S1 are sensitive nodes because the sensitive nodes of an integrated circuit are those in the surroundings of the reverse-biased drain junctions of an OFF transistor [11]. Due to the symmetry of the HRLP16T cell, we only analyze the case that the cell stores 0.…”