Characterization of defect traps in SiO2 thin films influence of temperature on defects

Rosaye, Jean-Yves; Kurumado, Norihiko; Sakashita, Mitsuo; Ikeda, Hiroya; Sakai, Akira; Mialhe, P.; Charles, J.‐P.; Zaima, Shigeaki; Watanabe, Yurihiko

doi:10.1016/s0026-2692(02)00004-6

Cited by 8 publications

(8 citation statements)

References 23 publications

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“…Also, the generation process of oxide trapped charges and impurities at the Si/SiO 2 interface is thermally activated; thus leads to the production of interface states and a distribution of oxide defects near the interface [12]. As result, V th decreases at high temperature [13,14]. Fig.…”

Section: Resultsmentioning

confidence: 99%

Temperature effect on an N‐channel commercial VDMOSFET transistor

Abboud

Salame

Cuminal

et al. 2011

Phys. Status Solidi (c)

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High temperature effect on MOSFET devices was evaluated by exposing the silicon devices to a temperature value above the normal operating range in order to study the device behavior under extreme conditions. Measurements show an increasing in the saturation drain‐source current and the reverse drain‐source current with temperature while the transistor threshold voltage and the diffusion voltage of the integrated pn junction were decreased. The carrier's mobility shows an increasing with temperature while the drain‐source on‐resistance was decreased. Switching times are also investigated as function of temperature and important variations are obtained on the device turn‐on and turn‐off times. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Section: Resultsmentioning

confidence: 99%

Temperature effect on an N‐channel commercial VDMOSFET transistor

Abboud

Salame

Cuminal

et al. 2011

Phys. Status Solidi (c)

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“…These defects are very near the interface, thus the fast state traps are able to exchange charge with the semiconductor in a very short time. They have energy states close to the Fermi energy E F and are located mainly within the silicon forbidden band gap (Rosaye et al , 2002). It may be valid to introduce the presence of additional mobile charges resulting from the breaking of bonds at the Si‐SiO 2 interface.…”

Section: Resultsmentioning

confidence: 99%

Temperature dependence of silicon power MOSFETs switching parameters

Habchi

Salame

Nsouli³

et al. 2006

Microelectronics International

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If you would like to write for this, or any other Emerald publication, then please use our Emerald for Authors service information about how to choose which publication to write for and submission guidelines are available for all. Please visit www.emeraldinsight.com/authors for more information. About Emerald www.emeraldinsight.comEmerald is a global publisher linking research and practice to the benefit of society. The company manages a portfolio of more than 290 journals and over 2,350 books and book series volumes, as well as providing an extensive range of online products and additional customer resources and services.Emerald is both COUNTER 4 and TRANSFER compliant. The organization is a partner of the Committee on Publication Ethics (COPE) and also works with Portico and the LOCKSS initiative for digital archive preservation. AbstractPurpose -This paper presents measurements of device switching parameters performed on a commercial power MOSFET under high temperature conditions, along with the inverse and direct source-drain current. Design/methodology/approach -Device temperature was linearly increased from 20 to 3008C. Switching times were measured by monitoring the current waveforms when the device was turned off and on. The gate was biased by a 10 V square signal while a 50 V DC bias was applied between the drain and source. The inverse current was measured under Vg ¼ 0V: Findings -The device response to being turned off becomes faster at high temperatures. The inverse leakage current is insignificant under 3008C but it increases rapidly after this limit. The direct saturation current increases with temperature for the same gate tension. These phenomena were associated to the thermal activation of defects. Originality/value -This paper offers information about switching performance of low cost commercial MOS devices in high temperature conditions. This information is essential in the microelectronic industry of harsh environments.

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“…For 5.4 nm thick samples, we took a better resolution to calculate fast‐state trap densities, that is to say, a sweep rate of 0.01 V/s because of the necessity to calculate small density values. Oxide samples of thickness 5.4 nm have very low defect densities, about 10 10 cm −2 (Rosaye et al , 2002). In these examples, experimental determination will not be easy with the classical quasi‐static C ‐ V method (High Low Frequency C ‐ V method: HLFCV) because only over‐estimated values can be found due to the limit fast‐state trap detection error.…”

Section: High Temperature Slow‐state Relaxationmentioning

confidence: 99%

“…We explain these results because of migration of hydrogen species. For the slow‐state trap relaxation, we can, at first, easily think of another high‐electric field, which induces Si‐H dissociation in the oxide, accompanied by a production of a “neutral species X” near the Si‐SiO 2 interface and we have developed a model to explain this relaxation microscopically (Rosaye et al , 2002). This mechanism can occur in oxynitrides because of same or similar oxide degradation mechanisms (Novkovski, 2002).…”

Section: High Temperature Slow‐state Relaxationmentioning

confidence: 99%

“…Next, by injection at different temperatures, we have investigated the creation mechanism of interface states and oxide defects. Our new method (Rosaye, 2001; Rosaye et al , 2001, 2002) proves to be useful to obtain the new properties of defects, such as their cross‐sections versus temperature and the relations between them in MOS devices. The defect creation activation energy is obtained from Arrhenius plots.…”

Section: Introductionmentioning

confidence: 99%

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Defect evolutions with different temperature injections in MOSFETs

Rosaye

Mialhe²,

Charles³

2003

Microelectronics International

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The present experiments are intended to help characterize defects in very thin MOS oxide and at its Si/SiO2 interface using a temperature‐dependent electrical characterization method, high low temperature capacitance voltage method and, especially, to investigate high temperature range. Oxide‐fixed traps are differentiated from slow‐state traps and from fast‐state traps by evaluating their electrical behaviour at different temperatures. The analysis points out the excess current after Fowler Nordheim electron injection based on hole generation, trapping, and hopping transport at high temperatures. The defect relaxation property versus temperature is investigated and defect relaxation activation energies are calculated. Creation mechanisms of interface states are especially identified by injection at different temperatures and these are compared with the other two kinds of defects. Fast‐state traps and all defect cross‐sections are calculated along and their creation activation energies are determined from Arrhenius plots.

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Characterization of defect traps in SiO2 thin films influence of temperature on defects

Cited by 8 publications

References 23 publications

Temperature effect on an N‐channel commercial VDMOSFET transistor

Temperature effect on an N‐channel commercial VDMOSFET transistor

Temperature dependence of silicon power MOSFETs switching parameters

Defect evolutions with different temperature injections in MOSFETs

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