Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

Kerber, A.; Maitra, K.; Majumdar, Amlan; Hargrove, M.; Carter, R.J.; Cartier, E.

doi:10.1109/ted.2008.2004853

Cited by 77 publications

(30 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is seen that the ΔV T recovery for all stress times follows a log(t) dependence. This behavior has been previously observed and has pointed to the suggestion that PBTI recovery is associated with electron detrapping via back tunneling through the IL into the inversion channel [8]. However, we are presenting below some experimental data that can not easily be rationalized by this assumption.…”

Section: Pbti Fractional Recovery Vs Il Thickness (Uninterrupted supporting

confidence: 58%

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

Ioannou

Cartier

Wang

et al. 2010

2010 IEEE International Reliability Physics Symposium

View full text Add to dashboard Cite

The impact of SiO 2 interfacial layer (IL) thickness on the Positive Bias Temperature Instability (PBTI) is investigated for nMOSFETs with an IL/High-K/metal/poly-Si gate stack architecture. Results from extensive PBTI measurements using three different measurement methodologies consistently demonstrate that thickening the IL results in threshold voltage (V T ) instability reduction and thus significantly enhances PBTI device lifetime. The voltage acceleration is found to increase with thicker IL, while the PBTI fractional recovery is independent of the IL thickness, providing new insights into the PBTI buildup and recovery mechanisms.

show abstract

Section: Pbti Fractional Recovery Vs Il Thickness (Uninterrupted supporting

confidence: 58%

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

Ioannou

Cartier

Wang

et al. 2010

2010 IEEE International Reliability Physics Symposium

View full text Add to dashboard Cite

show abstract

“…Impact on V t instability, inversion charge mobility, etc. has been demonstrated [2], [3]. On the other hand, evidence showed that the newly-generated bulk traps during NBTI stress also play an important role in the NBTI degradation [4] [5].…”

Section: Introductionmentioning

confidence: 99%

Evidence for the transformation of switching hole traps into permanent bulk traps under negative-bias temperature stressing of high-k P-MOSFETs

Gao

Ang

Young³

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

View full text Add to dashboard Cite

Under a given stress field, the recoverable component (R) for HfO 2 p-MOSFET appears almost constant at lower temperatures but shows a progressive decrease at higher temperatures. Similar conclusion can also be obtained for HfSiON p-MOSFET. Evidence shows that the decrease in R is due to its transformation into a more permanent form (P). We show that those switching hole traps (SHTs) responsible for the R share the same origin as a portion of bulk traps responsible for the stress induced leakage current (SILC) and 1/f noise of the high-k gate p-MOSFET. When the density of SHTs is constant, no increase in 1/f noise and SILC, i.e. no apparent generation of bulk traps, is observed after NBTI stress. An increase in the SILC and 1/f noise, which implies the generation of bulk traps, is observed when part of these SHTs are transformed into relatively permanent bulk traps, allowing them to be sensed by the slow SILC and 1/f noise measurements.

show abstract

“…Readings of the source and the meter outputs were recorded by the analog-digital converter (ADC) terminal of the PCI card. The conversion time for the ADC channel is <30μs while that for the DAC channel is <5μs [11] which comfortably enables ramp rates (RR) of 10V/s for the VRS test.…”

Section: Resultsmentioning

confidence: 99%

“…Full intermittent circuit characteristics were obtained during the VRS test using inverting operational amplifier circuits as "source" and a buffer amplifier as "meter". For cross-coupled inverter a CMOS switch is employed to alter the "source" and "meter" termination of the SNL and SNR nodes (for details see [11]). Fig.…”

Section: Discussionmentioning

confidence: 99%

“…For breakdown studies in circuits, single stage CMOS inverters, inverter chains (not discussed), and crosscoupled inverter (CCI) circuits used in SRAM cells, were investigated. The novel VRS characterization was performed with the fast Peripheral Component Interconnect (PCI) card based data acquisition technique for full intermittent circuit characterization during the sense measurement [11,12]. In addition to the VRS technique, the conventional CVS characterization method was applied to verify the time evolution of breakdown current transients in discrete devices.…”

Section: Methodsmentioning

confidence: 99%

See 1 more Smart Citation

Impact of TDDB in MG/HK devices on circuit functionality in advanced CMOS technologies

Kerber

Lipp

Trentzsch

et al. 2011

2011 International Electron Devices Meeting

View full text Add to dashboard Cite

The impact of time-dependent dielectric breakdown (TDDB) in metal gate (MG) / high-k (HK) devices on CMOS circuit functionality is examined using a novel fast PCI card based characterization setup. Detailed information on the role of the driver resistance on circuit failure is provided. By comparing breakdown in circuits to TDDB characteristics in discrete devices, it is shown that soft breakdown in the cross-coupled inverter circuit is well-correlated with soft breakdown in discrete CMOS devices. However, in all cases studied, it is observed that immediate circuit failure during high voltage stress is prevented by the resistance of the driver element. Implications of these findings on circuit lifetime assessment are discussed.

show abstract

Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

Cited by 77 publications

References 15 publications

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

Evidence for the transformation of switching hole traps into permanent bulk traps under negative-bias temperature stressing of high-k P-MOSFETs

Impact of TDDB in MG/HK devices on circuit functionality in advanced CMOS technologies

Contact Info

Product

Resources

About