Characterization of GaAs-based n-n and p-n interface junctions prepared by direct wafer bonding

Abstract

Electron mobility, Hall scattering factor, and sheet conductivity in AlGaN/AlN/GaN heterostructures J. Appl. Phys. 110, 113713 (2011) Reduction of the potential energy barrier and resistance at wafer-bonded n-GaAs/n-GaAs interfaces by sulfur passivation J. Appl. Phys. 110, 104903 (2011) Diameter reduction of nanowire tunnel heterojunctions using in situ annealing Appl. Phys. Lett. 99, 203101 (2011) Substrate nitridation induced modulations in transport properties of wurtzite GaN/p-Si (100) heterojunctions grown by molecular beam epitaxy J. Appl. Phys. 110, 093718 (2011) Characteristics of a-GaN films and a-AlGaN/GaN heterojunctions prepared on r-sapphire by two-stage growth process

GaAs solar cell on Si substrate with good ohmic GaAs/Si interface by direct wafer bonding

“…Considering the resistance chain shown in Fig. 2(b), the R interface of p-GaAs/n-Si was estimated [16]. A total resistance (R total ) is composed of a resistance between the contact tip and the contact pad (R tip ) and a contact resistance for GaAs (R c, top ), Si (R c, bottom ), and a spreading resistance (R spread ) and a bulk resistance of GaAs and Si and R interface .…”

“…However, due to a large lattice mismatch, epitaxially grown III-V on a Si substrate exhibits poor performance. To circumvent this issue, many studies have reported on III-V wafers bonded to Si structures using a direct wafer bonding [13][14][15][16][17][18][19]. Here, for the integration of III-V device to the Si, an important consideration is the difference of thermal expansion coefficient between the GaAs and the Si.…”

“…However, with III-V semiconductor bonding, it is not easy to achieve an ohmic interface [17,19]. Even when good ohmic interfaces were reported by some groups, the bonding temperatures were above the acceptable level (over 700°C) [15,16,18]. This can induce material defects in the III-V semiconductor itself and also induce a high strain in the III-V layer on Si substrate.…”

Low-Temperature III–V Direct Wafer Bonding Surface Preparation Using a UV-Sulfur Process

“…4 Often, annealing at elevated temperatures (>600°C) for times in excess of 30 min with large compressive forces must be employed to break up the interfacial oxide layer to form better contact between the III-V layers. 5 These harsh processing conditions can be undesirable for processed samples with a limited thermal process budget. Lian et al demonstrated that temperatures of at least 550°C for 1 h are required for AlGaAs/ GaAs/GaN heterojunction bipolar transistors (HBTs) formed by wafer fusion methods, yet that the HBTs suffer gain degradation at annealing temperatures above 450°C.…”

Strain analysis of InP/InGaAsP wafer bonded on Si by X-ray double crystalline diffraction

“…Over the past 10 years, direct wafer bonding has received considerable attention for releasing the restrictions of lattice matching imposed by epitaxial growth and opening new degrees of freedom for the design of semiconductor devices [1][2][3][4][5][6][7][8][9][10]. During the wafer bonding process, thermal treatment is a very important step, which increases the surface energy and bonding strength of the bonded wafers [11].…”