Low-Temperature III–V Direct Wafer Bonding Surface Preparation Using a UV-Sulfur Process

Jackson, Michael J.; Chen, Limin; Kumar, Ankit; Yang, Yang; Goorsky, Mark S.

doi:10.1007/s11664-010-1397-8

Cited by 15 publications

(9 citation statements)

References 22 publications

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“…In addition, the use of monolayers and/or hydrophilic dielectric layers can relax the requirements for surface smoothness of the wafers [166,167]. Finally, we note that III-V wafer bonding can also be accomplished using sulphide-treated surfaces [168][169][170], but these methods are not covered here.…”

Section: Wafer Bonding Techniques For Long Wavelength Infraredmentioning

confidence: 99%

Optically pumped VECSELs: review of technology and progress

Guina

Rantamäki

Härkönen

2017

J. Phys. D: Appl. Phys.

205

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Section: Wafer Bonding Techniques For Long Wavelength Infraredmentioning

confidence: 99%

Optically pumped VECSELs: review of technology and progress

Guina

Rantamäki

Härkönen

2017

J. Phys. D: Appl. Phys.

205

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“…Wafer bonding between two substrate materials relies [2] on the following parameters: (a) the materials being bonded (mismatch of coefficient of thermal expansion (CTE)), (b) surface conditions (flatness, smoothness and cleanliness), and (c) bonding environment (bonding temperature, and applied force or pressure). The creation of a bonded interface between the wafers is usually performed at room temperature [3], with further multi-stage annealing steps performed to increase the bond strength, and make the interface more conductive [4].…”

Section: Wafer Bonding Requirementsmentioning

confidence: 99%

“…The first was made by bonding together two heavy doped n++ GaAs wafers, while the other structure was made using heavy doped p++ GaAs wafers. The GaAs wafer bonding process used in this study is detailed elsewhere [3,4]. Briefly, the surfaces of the bare wafers were cleaned with acetone and DI water to remove particles.…”

Section: Gaas Wafer Bondingmentioning

confidence: 99%

High Resolution Double-Crystal X-ray Diffraction Imaging for Interfacial Defect Detection in Bonded Wafers

Sharma

Goorsky

2013

ECS Trans.

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Wafer bonding is used for the integration of heterogeneous semiconductor materials, without the constraints of lattice constant or crystal structure mismatch. The most important aspect of such bonding is the surface flatness and the absence of particles in the bonded interface. It is very important to identify these particles, which can further result in poor bonding. The most common method for identifying has been infra-red (IR) imaging, but it is limited to materials which are transparent in the operating region of the CCD camera. Also, the resolution of IR image is low. X-ray topography or X-ray diffraction imaging (XRDI) has been identified as a very sensitive and high resolution imaging technique, capable of resolving variations due to very small particles within both the bonded and the unbonded areas. It also allows for imaging of samples which are opaque to IR, like heavily doped wafers that are used for solar cell applications. Wafer bondingDirect wafer bonding allows for the integration of heterogeneous semiconductor materials, without the constraints of lattice constant or crystal structure mismatch. Direct wafer bonding is based on intermolecular interactions -including Van der Waals forces, hydrogen bonds and strong covalent bonds [1]. Main applications are for bonding of Si substrates for heat sinking of GaN HEMTs, creation of multi-junction solar cells (GaAs/InGaAs etc), creation of SOI wafers (Smartcut, ELTRAN, Nanocleave), and production of microelectronic (MEMS, NEMS) devices [1]. Wafer Bonding RequirementsWafer bonding between two substrate materials relies [2] on the following parameters: (a) the materials being bonded (mismatch of coefficient of thermal expansion (CTE)), (b) surface conditions (flatness, smoothness and cleanliness), and (c) bonding environment (bonding temperature, and applied force or pressure). The creation of a bonded interface between the wafers is usually performed at room temperature [3], with further multi-stage annealing steps performed to increase the bond strength, and make the interface more conductive [4].Particles present on the surface cause problems for the fusion bonding process. Even sub-micron size particles can create voids which prevent bond from occurring in that local region. However, such voids can be reduced in size after annealing the wafers. The voids created due to trapped gas cannot be removed even after a long annealing process. 10.1149/05007.0091ecst ©The Electrochemical Society ECS Transactions, 50 (7) 91-96 (2012) 91 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 131.215.225.9 Downloaded on 2015-07-12 to IP

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“…A sulfur-based surface treatment prior to bonding was found to reduce the thickness of unfavorable oxides at the interface, reducing the post-bonding thermal and compressive force requirements, and promoting the ability to bond large (100 mm diameter) wafers. Integration of III-V heterostructures by direct wafer bonding prevents the growth of threading dislocations in epitaxial layers by allowing two lattice mismatched materials to be directly integrated via secondary Van der Waals forces without any induced strain (1,2,3,4).…”

Section: Introductionmentioning

confidence: 99%

Effects of Miscut Substrates on Electrical Conductivity Across InP and GaAs Wafer-Bonded Structures

et al. 2014

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Wafer bonding of GaAs and InP using an (NH 4 ) 2 S treatment are investigated for the effect of the wafer offcut angle on the electrical conductivity of wafer-bonded III-V interfaces. HRTEM and STEM are used to confirm the misorientation of the bonded samples and to compare the interface morphology across the range of relative misorientations. A line ratio at the interface shows that the well-bonded crystalline regions to amorphous oxide inclusions is consistent across all bonded samples, indicating that the degree of misorientation does not affect the level of interface recrystallization at high temperatures. Fitting the zero-bias conductance over a range of temperatures reveals an increase in barrier heights for samples with greater than 4° misoriented bonded pairs. This demonstrates that the out-of-plane relative surface misorientation is a critical parameter to be monitored and thus any in-plane twist as well in order to achieve superior electrical conductivity in direct-bonded multijunction solar applications.

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Low-Temperature III–V Direct Wafer Bonding Surface Preparation Using a UV-Sulfur Process

Cited by 15 publications

References 22 publications

Optically pumped VECSELs: review of technology and progress

Optically pumped VECSELs: review of technology and progress

High Resolution Double-Crystal X-ray Diffraction Imaging for Interfacial Defect Detection in Bonded Wafers

Effects of Miscut Substrates on Electrical Conductivity Across InP and GaAs Wafer-Bonded Structures

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