Characterization of silicon nanowire transistor

Abstract

This paper analyses the temperature sensitivity of Silicon Nanowire Transistor (SiNWT) depends on the diameter (D.ch) of channel. In addition, it also investigates the possibility of utilizing SiNWT as a Nano-temperature sensor. The MuGFET simulation tool has been utilized to conduct a comprehensive simulation to evaluate both electrical and temperature characteristics of SiNWT. Current-voltage characteristics with different values of temperature and with a varying diameter of the Nano wire channel (D.ch = 80, 40, 20 and 10 nm), were simulated. Diode operating mode connection of the transistor is suggested for measuring the temperature sensitivity of SiNWT. As simulation results demonstrated, the best temperature sensitivity was occurred at lower temperature with increasing the channel diameter. We also illustrate the impact of varying temperature and channel diameter on electrical characteristics of SiNWT including, Subthreshold Swing (SS), Threshold voltage (V.th), and Drain-induced barrier lowering (DIBL), which were proportionally increased with the operating temperature.

The impact of channel fin width on electrical characteristics of Si-FinFET

“…The simulation tools have an ability to support the research fields for more characterization the Nano-dimensional devices [21]. As well, simulation tools can define the nanodevice failure, in addition, retrenchment the costs of fabrication of these nano-devices in the Nano dimensions field [22], [23].…”

Modeling and characterization of optimal nano-scale channel dimensions for fin field effect transistor based on constituent semiconductor materials

“…Nano-electronic applications have benefited enormously from substantial advancements in the emerging nanotechnology industry. The tremendous downscaling of transistor dimensions has enabled the placement of over 100 million transistors on a single chip, thereby resulting in reduced cost, increased functionality, and enhanced performance of integrated circuits (ICs) [1]- [3]. However, reducing the size of conventional planar transistors would be exceptionally challenging due to electrostatic leakages and other fabrication issues [4], [5].…”

Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling

“…However, the essential physical limitation of MOSFET that is to scale them at the submicron region is the pursuing short channel effects (SCEs) [1]. The silicon nanowire transistor is also used as a candidate device which has the excellent gate controlled and highly influenced electrical behavior to overcome the problems caused by short channel effects [2][3][4][5]. In the last decade, the rapid development in shrinking of semiconductors device led to the short channel effects as very harsh problem such as increasing drain induced barrier lowering (DIBL), and many research have been done in the last decade to find the substitutive device structure for striving improvements.…”