Characterization of submicron ring oscillator using the first order design equations

2018

Circuit Theory & Apps

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In this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate-based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate-based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op-amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage-controlled oscillator is of conventional current-starved type. The divider makes use of true single-phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage-controlled oscillator.KEYWORDS blind zone, charge pump (CP), dead zone, divider, loop filter, phase frequency detector (PFD), voltagecontrolled oscillator (VCO)

Section: Simulation Resultsmentioning

confidence: 99%

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

2018

Circuit Theory & Apps

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“…To verify the equation that got derived, simulation of the ring oscillator's circuit is performed in TSMC 180 nm, utilizing Cadence Virtuoso. The earlier work of the authors on the characterization of ring oscillator was performed by keeping the beta ratio fixed at 2.3 [18,19] . In this particular work, the design is extended to encompass the asymmetric MOSFET dimensions, so as to have a width-independent approach.…”

Section: Circuit Simulation and Resultsmentioning

confidence: 99%

“…However, for all the devices, the channel lengths are chosen as the same value; i.e., L p = L n = L. For TSMC 180 nm process, the values of SPICE parameters are, μ n = 2.6365 × 10 −2 m 2 /(V•s), μ p = 1.1498 × 10 −2 m 2 /(V•s), V tn = 0.372 V and V tp = −0.387 V. Substituting these values in Eqs. (18) and ( 19) and choosing V DD = 1.8 V,…”

Section: When One Mosfet Is In Linear Region and The Other Is In Cutoffmentioning

confidence: 99%

Frequency equation for the submicron CMOS ring oscillator using the first order characterization

2018

J. Semicond.

By utilizing the first order behavior of the device, an equation for the frequency of operation of the submicron CMOS ring oscillator is presented. A 5-stage ring oscillator is utilized as the initial design, with different Beta ratios, for the computation of the operating frequency. Later on, the circuit simulation is performed from 5-stage till 23-stage, with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively. It is noted that the output frequency is inversely proportional to the square of the device length, and when the value of Beta ratio is used as 2.3, a difference of 3.64% is observed on an average, in between the computed and the simulated values of frequency. As an outcome, the derived equation can be utilized, with the inclusion of an empirical constant in general, for arriving at the ring oscillator circuit’s output frequency.

“…Thus, for the two states of output, the resistances and the capacitances that are required for the computation of stage delay are computed. This is performed with respect to each node, by computing the R and C individually [32, 33]. Finally, when W p / W n = 2.3, the output frequency of the ring oscillator is expressed as

f_{osc} = \frac{1}{2000 N L^{2}}

Equation (4) helps the circuit designer during simulation, for arriving at the required value of the frequency.…”

Section: Designs Of Cp and Vcomentioning

confidence: 99%

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

IET Circuits, Devices & Systems

2020

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In this article, a novel design is presented, for an Integer-N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.