Characterization of the Total Charge and Time Duration for Single-Event Transient Voltage Pulses in a 65-nm CMOS Technology

Li, Zheyi; Berti, L.; Wouters, Jan; Wang, Jialei; Leroux, Paul

doi:10.1109/tns.2022.3141070

Cited by 6 publications

(4 citation statements)

References 27 publications

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“…Figure 2(a) illustrates the probability of occurrence for different event types resulting from a SET injection into a random node of the RISC-V core, including the clock tree, at two different clock frequencies. The pulse duration distribution depicted in figure 2(b) reflects the expected duration of single-event transients in a 65 nm technology subjected to heavy ion irradiation with a linear energy transfer of 30 MeV cm 2 /mg [6]. The even with a 1000 ps SET duration covering 5% of the total clock cycle when operating at 50 MHz.…”

Section: Transient-induced Single Event Upsetsmentioning

confidence: 94%

Fault tolerance evaluation study of a RISC-V microprocessor for HEP applications

Walsemann,

Karagounis,

Stanitzki

et al. 2024

J. Inst.

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The utilization of a radiation-hard microprocessor or a System-on-Chip (SoC) design methodology significantly benefits the future design of ASICs for HEP experiments. To evaluate the fault tolerance of a radiation-hard design, it is important to obtain detailed information on the soft error rate and contributing factors. This article presents a simulation-based approach to investigate the effects of faults induced by single event transients in a microprocessor based on the open RISC-V instruction set architecture.

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Section: Transient-induced Single Event Upsetsmentioning

confidence: 94%

Fault tolerance evaluation study of a RISC-V microprocessor for HEP applications

Walsemann,

Karagounis,

Stanitzki

et al. 2024

J. Inst.

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“…3 (a) and (b) are based on victim circuit structures reported in Ref. [21]. The structure for nSET was composed of one on-state pMOSFET and 30 off-state nMOSFETs connected in parallel.…”

Section: Target Structuresmentioning

confidence: 99%

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation

FURUTA,

SUGITANI,

NAKAJIMA

et al. 2024

IEICE Trans. Electron.

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Radiation-induced temporal errors become a significant issue for circuit reliability. We measured the pulse widths of radiationinduced single event transients (SETs) from pMOSFETs and nMOSFETs separately. Test results show that heavy-ion induced SET rates of nMOS-FETs were twice as high as those of pMOSFETs and that neutron-induced SETs occurred only in nMOSFETs. It was confirmed that the SET distribution from inverter chains can be estimated using the SET distribution from pMOSFETs and nMOSFETs by considering the difference in load capacitance of the measurement circuits.

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“…Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices are widely applied in satellite electronic systems owing to their low power consumption, high integration, and low production cost [1,2]. However, CMOS devices are often subject to collisions with high-energy protons and heavy ions from the cosmic space environment.…”

Section: Introductionmentioning

confidence: 99%

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Xin

Zhu

et al. 2023

Electronics

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Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

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Characterization of the Total Charge and Time Duration for Single-Event Transient Voltage Pulses in a 65-nm CMOS Technology

Cited by 6 publications

References 27 publications

Fault tolerance evaluation study of a RISC-V microprocessor for HEP applications

Fault tolerance evaluation study of a RISC-V microprocessor for HEP applications

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

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