Characterization of thermally oxidized Ti∕SiO2 gate dielectric stacks on 4H–SiC substrate

Abstract

The structural and electrical characteristics of thermally oxidized Ti∕SiO2 gate dielectric stacks on 4H–SiC substrates have been investigated. X-ray photoelectron spectroscopy shows a good stoichiometry of TiO2 films formed by thermal oxidation of evaporated Ti. No evidence of the formation of titanium silicide at the surface as well as in the interfacial layer was observed. Electrical measurements show, in particular, no signature of an increase in interface state density towards the conduction band edge of 4H–SiC. The improved leakage current with higher breakdown field of 11MV∕cm makes TiO2∕SiO2 stacks a potential gate insulator for high-power SiC devices.

Defect profiles in semiconductor structures

“…VEPAS suggests that the concentration of vacancies decreases as the TiO 2 growth temperature is increased in the range 700 to 1000 ºC; it is proposed that the optimal electrical performance for films grown at 800 ºC reflects a balance between decreasing vacancy concentration and increasing grain boundary formation. Electrical tests [30] showed well-behaved high-frequency C-V and σ-V characteristics of the stack layers, and an im[proved effective breakdown field of ~11 MV/cm.…”

Positron spectroscopy of high‐k dielectric films on SiC

“…However, because the band gap of dielectrics decreases as k increases [7], there is a low band offset at the SiC -dielectric interface. This fundamental limitation may be overcome by introducing an SiO 2 interlayer [8], and first studies of the electrical and physical properties of high-k TiO 2 /SiO 2 insulating stacks on 4H-SiC substrates have recently been reported [9] which, while encouraging, remain far from ideal. Physical mechanisms for such effects as leakage currents are well understood in conventional SiO 2 technology but are relatively uninvestigated in these novel dielectrics. )…”

On the robustness of ultra-high voltage 4H-SiC IGBTs with an optimized retrograde p-well

“…High-κ dielectrics are proposed to improve the performance of SiC power devices at high-voltages [17][18][19][20]. However, due to significant lattice mismatch, high-quality dielectric/SiC interfaces are particularly challenging to achieve in practice, often exhibiting a high density of defects (>10 11 eV -1 .cm -2 ) [19,20], which ultimately lead to poor channel mobilities.…”