Characterization of Wafer-Level Thermocompression Bonds

Tsau, Christine H.; Spearing, S. Mark; Schmidt, M.A.

doi:10.1109/jmems.2004.838393

Cited by 93 publications

(50 citation statements)

References 11 publications

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“…However, when MEMS realization requires also electrical contact through the cavity, thermocompression bonding appears as a good candidate. The use of gold material for the electrical contacts and for the cavity sealing is widespread because of its advantages as very good electrical conductivity, low temperature process and very stable physical properties [1][2][3][4][5][6]. The present works is focused on the realization and qualification of micro-cavities with electrical contacts using Au/Au thermocompression wafer level bonding.…”

Section: Introductionmentioning

confidence: 99%

Hermetic Cavities Using Gold Wafer Level Thermocompression Bonding

Charlot

Pons

Dilhan

et al. 2017

Proceedings of Eurosensors 2017, Paris, France, 3–6 September 2017

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This paper presents the study of gold/gold thermocompression bonding at silicon wafer level. The first samples contains sealing rings and electrical pads, and are characterized on pull, and shear test showing bond strength similar to silicon/glass anodic bonding (10 MPa-80 MPa). A sealed cavity and a piezoresistor on a 30 µm-thick silicon membrane are added in the second samples. Helium test, membrane deflection and piezoresistor signal monitoring after aging 14 days at 250 °C confirm the vacuum stability inside the cavity after bonding.

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Section: Introductionmentioning

confidence: 99%

Hermetic Cavities Using Gold Wafer Level Thermocompression Bonding

Charlot

Pons

Dilhan

et al. 2017

Proceedings of Eurosensors 2017, Paris, France, 3–6 September 2017

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“…Unfortunately, current bonding technologies, such as fusion bonding [9] or thermo-compression bonding [10], do not provide the following properties at the same time:…”

Section: Introductionmentioning

confidence: 99%

Low-Temperature Bonding for Silicon-Based Micro-Optical Systems

Howlader

Deen

2015

Photonics

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Abstract:Silicon-based integrated systems are actively pursued for sensing and imaging applications. A major challenge to realize highly sensitive systems is the integration of electronic, optical, mechanical and fluidic, all on a common platform. Further, the interface quality between the tiny optoelectronic structures and the substrate for alignment and coupling of the signals significantly impacts the system's performance. These systems also have to be low-cost, densely integrated and compatible with current and future mainstream technologies for electronic-photonic integration. To address these issues, proper selection of the fabrication, integration and assembly technologies is needed. In this paper, wafer level bonding with advanced features such as surface activation and passive alignment for vertical electrical interconnections are identified as candidate technologies to integrate different electronics, optical and photonic components. Surface activated bonding, superior to other assembly methods, enables low-temperature nanoscaled component integration with high alignment accuracy, low electrical loss and high transparency of the interface. These features are preferred for the hybrid integration of silicon-based micro-opto-electronic systems. In future, new materials and assembly technologies may emerge to enhance the performance of these micro systems and reduce their cost. The article is a detailed review of bonding techniques for electronic, optical and photonic components in silicon-based systems.

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“…[1][2][3][4] Furthermore, and maybe the most attractive, 5 this technology enables the possibility of heterogeneous integration of disparate functional blocks, such as micro-electro-mechanical system (MEMS) sensors and complementary metal-oxide-semiconductor (CMOS) circuit integration in a vertical and seamless way, 6 as well as in InP-Si heterogeneous direct bonding to enhance the performance of Si photonic integrated devices. 7 A great number of materials have been applied to achieve wafer-level bonding for 3D integration circuit (IC) applications; the most popular include polymer adhesive materials, 8,9 intermetallic compounds, 10,11 diffusion metal materials (such as gold, 12 aluminum, 13 and copper,) 14 and silicon oxide. 15 Amongst these different materials, copper and oxide are most attractive as they are widely used as the interconnectors and interlayer dielectrics based on CMOS backend processing.…”

Section: Introductionmentioning

confidence: 99%

High-κ Al2O3 material in low temperature wafer-level bonding for 3D integration application

Fan

Tan

2014

AIP Advances

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This work systematically investigated a high-κ Al2O3 material for low temperature wafer-level bonding for potential applications in 3D microsystems. A clean Si wafer with an Al2O3 layer thickness of 50 nm was applied as our experimental approach. Bonding was initiated in a clean room ambient after surface activation, followed by annealing under inert ambient conditions at 300 °C for 3 h. The investigation consisted of three parts: a mechanical support study using the four-point bending method, hermeticity measurements using the helium bomb test, and thermal conductivity analysis for potential heterogeneous bonding. Compared with samples bonded using a conventional oxide bonding material (SiO2), a higher interfacial adhesion energy (∼11.93 J/m2) and a lower helium leak rate (∼6.84 × 10−10 atm.cm3/sec) were detected for samples bonded using Al2O3. More importantly, due to the excellent thermal conductivity performance of Al2O3, this technology can be used in heterogeneous direct bonding, which has potential applications for enhancing the performance of Si photonic integrated devices.

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Characterization of Wafer-Level Thermocompression Bonds

Cited by 93 publications

References 11 publications

Hermetic Cavities Using Gold Wafer Level Thermocompression Bonding

Hermetic Cavities Using Gold Wafer Level Thermocompression Bonding

Low-Temperature Bonding for Silicon-Based Micro-Optical Systems

High-κ Al2O3 material in low temperature wafer-level bonding for 3D integration application

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