Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

“…Therefore, the main operation regime for the heavily doped devices (JL) is usually bulk (V TH < V GS < V FB ), due to the large V FB -V TH difference, and for slightly or highly doped devices (AM) is accumulation (V GS > V FB ). Operation in the bulk regime has the advantage of less degradation of carrier mobility due to the perpendicular field (conduction at the middle part of the channel) [10] but suffering from a non-straight forward analytical model in this region [11].…”

“…3 can be seen as a degenerate double-gate architecture and therefore, an estimation of the accumulation current can be obtained from [11]. Indeed, noting that in the linear accumulation regime (V DS < V GS -V FB ), the log terms can be discarded in the charge vs. potential and retaining only the highest order term in Eqs.…”

“…Indeed, noting that in the linear accumulation regime (V DS < V GS -V FB ), the log terms can be discarded in the charge vs. potential and retaining only the highest order term in Eqs. (16), (22), and (24) in [11] (an assumption valid only in strong accumulation), we obtain (using source as a reference):…”

“…Since the accumulation-mode and junctionless transistors work in a simple MOSFET-like manner only above the flat-band voltage but not above the threshold voltage [11], direct extraction of the flat-band voltage as a key MOSFET parameter from the characterization data seem to be pretty necessary. At the first glance, the V FB value is expected to be extracted using the intersect of the two quasi-straight lines above the threshold voltage corresponding to the bulk and accumulation regimes in the transfer characteristic [25] or using I D / ffiffiffiffiffiffi g m p in the strong accumulation regime as an approximation [21,22].…”

The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling

“…The theoretical foundations of JL FETs with double-gate [3], analysis of turned on characteristics of JL nanowire FET at different drain voltages and the potential under various operating conditions [4], discrete doping-induced variability in junctionless nanowire MOSFETs using dissipative quantum transport simulations [5], the impact of random dopant fluctuation for several JL FinFET [6], et al can be searched. Furthermore, some modeling results such as theoretical model of the JL silicon-on-insulator (SOI) FET [7] and a charge-based model of DG MOSFETs [8] have been reported. Some groups studied the OFF-state behavior of JLTs, and showed the effect of BTBT on JLT operating in volume depletion in OFF state [2].…”