Charge-pumping characterization of SiO/sub 2//Si interface in virgin and irradiated power VDMOSFETs

Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

“…3 and 4, respectively. The charge pumping technique [14] yielded similar values of DN it , indicating that contribution from border traps was negligible. As can be seen, the initial NBT stress caused more significant buildup of oxide-trapped charge than that of interface traps, which is in line with our earlier observation on dominant role of oxide-trapped charge in shaping the DV T time dependencies in VDMOSFETs subjected to continuous NBT stress [9].…”

Isothermal and isochronal annealing experiments on irradiated commercial power VDMOSFETs

“…The boundaries of the so called CP active region are shown on the 1 MHz curve of a virgin device. Namely, the CP active region is defined by Vpp-AVG < V,, < VFCP [14], where Vpp and V,,", are CP threshold and flat-band voltages of the a-epi region of a device, respectively. The effect of oxide-trap charge is clearly visible in Fig.…”

“…The principle of the hasic technique [ l l ] restricts its applicability to devices that have a separate bulk contact, i.e. four terminal devices, However, recently Habas et al[14] proposed a modified CP experiment demonstrated its applicability in virgin and…”

Influence of Ionizing Radiation and Hot Carrier Injection on Metal-Oxide-Semiconductor Transistors

“…As the CP technique requires a separate outlet for the substrate, it could be concluded that it is not applicable for power VDMOS transistors, in which the p-bulk is technologically connected to the source. However, thanks to the very structure of these transistors [106], the CP technique is applicable in a somewhat altered form; as shown in Figure 7 [25,107]. It should be pointed out that VDMOS power transistor represents a parallel connection of a large number of cells (elementary transistor structures) with a large surface, which is especially suitable for the CP technique (higher level of current which is easier to measure).…”

“…meaning that ∆N it (CP) ≡ ∆N fst ). SST (with density ∆N sst ) located in the oxide, near the Si -SiO 2 interface are frequently called slow states (SS) [21], anomalous positive charge (APC) [25], switching oxide traps (SOT) [26] or border traps (BT) [24]. Finally, it should be pointed out that during the measurement by the SMG technique, ST exchange charges during the measurement meaning that in case of an n-channel MOS transistor (NMOS) these centres capture charges from the channel but releases them when the measurement is finished.…”