Charge Trapping &amp; NBTI in High k Gate Dielectric Stacks

Zafar, Sufi; Callegari, Alessando; Stathis, J. H.

doi:10.1149/1.2209307

Cited by 3 publications

(1 citation statement)

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“…Gate stack reliability can be evaluated by understanding the charge trapping behavior of the dielectric and its response to electrical stress. Charge trapping in high-κ gate oxides under different stress conditions is widely reported (21)(22)(23)(24)(25)(26)(27)(28)(29)(30)(31)(32)(33). Stress induced flat-band voltage shifts (34) and stress-induced leakage currents (SILC) (35) represent the robustness of these films.…”

Section: Introductionmentioning

confidence: 99%

Cyclic Plasma Treatment during ALD Hf_1-XZr_xO₂ Deposition

et al. 2014

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Effect of SPA Ar plasma on the reliability of intermediate plasma (DSDS) treated ALD Hf1-xZrxO2 samples with x=0, 0.31, 0.8 were investigated. The MOS capacitors (MOSCAP) were subjected to a constant field stress of 27.5 MV/cm in the gate injection mode and the stress-induced flat-band voltage shifts and stress induced leakage currents were monitored. The dielectric film deposited without any intermediate step (As-Dep), having the same number of ALD cycles as DSDS samples was used as the control sample. It was observed that plasma exposure enhances the quality of high-k film by reducing the number of intrinsic traps in the film and Zr addition further enhances the reliability. Breakdown characteristics also confirm this behavior. Electron affinity variation in HfO2 and ZrO2 and Zr variation seems to contribute to the improvement in DSDS Hf1-xZrxO2 (x=0.8) by suppressing the oxide trap formation as observed in the Weibull characteristics. DSDS Hf1-xZrxO2 with x=0.8, therefore, demonstrates a superior EOT downscaling ability and good reliability performance.

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