Abstract:This paper proposes a novel Gm−C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (ΣΔ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured re… Show more
“…The tuning range of the VCO is PLLs in Refs. [2] and [3], the proposed hybrid PLL achieves lower reference spur level. The sub-sampling technology is employed in Ref.…”
Section: Simulation and Experimental Resultsmentioning
confidence: 96%
“…Phase-locked loops (PLLs) have been widely applied to recover and synthesize the frequency and phase in versatile wireless devices and systems, including frequency synthesizers, clock generators, high-speed data communication, and power generation systems. [1][2][3][4][5] Low spur signal and fast locking time are two key requirements in nearly all applications of PLLs. The most straightforward way to suppress the reference spurs of a PLL is to reduce its loop bandwidth.…”
Hybrid phase-locked loop with fast locking time and low spur in a 0.18-µm CMOS process * Zhu Si-Heng(朱思衡) a) , Si Li-Ming(司黎明) a) † , Guo Chao(郭 超) a) , Shi Jun-Yu(史君宇) a) , and Zhu Wei-Ren(朱卫仁) b) a)
“…The tuning range of the VCO is PLLs in Refs. [2] and [3], the proposed hybrid PLL achieves lower reference spur level. The sub-sampling technology is employed in Ref.…”
Section: Simulation and Experimental Resultsmentioning
confidence: 96%
“…Phase-locked loops (PLLs) have been widely applied to recover and synthesize the frequency and phase in versatile wireless devices and systems, including frequency synthesizers, clock generators, high-speed data communication, and power generation systems. [1][2][3][4][5] Low spur signal and fast locking time are two key requirements in nearly all applications of PLLs. The most straightforward way to suppress the reference spurs of a PLL is to reduce its loop bandwidth.…”
Hybrid phase-locked loop with fast locking time and low spur in a 0.18-µm CMOS process * Zhu Si-Heng(朱思衡) a) , Si Li-Ming(司黎明) a) † , Guo Chao(郭 超) a) , Shi Jun-Yu(史君宇) a) , and Zhu Wei-Ren(朱卫仁) b) a)
“…Equation (19) is convenient for obtaining the parametric NU solution. The outline of this method is given in Appendix A [30][31][32][33][34][35] (21) and further using Eq. (A7), we have…”
Section: Energy Eigenvalues and Wave Functions Of The Spin Symmetric mentioning
confidence: 99%
“…On the other hand, the Dirac equation with PDM has been found to be very useful in studying some physical properties of various microstructures [11][12][13][14][15][16][17][18]. Recently, there has been increased interest in searching for analytical solutions of the Dirac equation with PDM and with constant mass under the spin and pseudospin (p-spin) symmetries [19][20][21][22][23][24][25]. In their recent works Hamzavi and Rajabi have studied Dirac equation in 1+1 dimensions with scalar-vector-pseudoscalar Cornell potential for spin-1/ 2 particle under spin and pseudospin symmetries [26].…”
We investigate the approximate solutions of the Dirac equation with the position-dependent mass particle in the Eckart potential field including the Coulomb tensor interaction by using the parametric Nikiforov-Uvarov method. Taking an appropriate approximation to deal with the centrifugal term, the Dirac energy states and the corresponding normalized two-spinor components of the wave function are obtained in closed form. Some special cases of our solution are investigated. Further, we present the correct solutions obtained via asymptotic iteration method which are in agreement with the parametric Nikiforov-Uvarov method results.
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