A 5.8‐GHz frequency synthesizer using wideband LC‐tank voltage‐controlled oscillator (VCO) for worldwide interoperability for microwave access applications with a 1.8 V voltage supply has been designed and successfully implemented in TSMC 0.18 μm CMOS process. In this proposed circuit, two important ideas are applied. First, a 3‐bit binary weighted capacitor array in the VCO is adopted to extend the tuning range and reduce the phase noise. Second, a class‐AB current mode logic is utilized in first divider stage to handle the high frequency signal. Measured results show that output frequency of VCO is tunable from 5.3 to 6.1 GHz corresponding to 14.1%, and phase noise is −110.2 dBc/Hz at 1 MHz offset, output power spectrum is −9.24 dBm at frequency of 5.73 GHz, power consumption is 32 mW, and including pads, chip area is 0.53 (0.82 × 0.65) mm2. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2931–2935, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26405

This paper proposes a novel Gm−C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta (ΣΔ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is −114.1 dBc/Hz with lower Gm−C bandwidth and −111.7 dBm/C with higher Gm−C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm−C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is −8.69 dBm at 5.68 GHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2

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