Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

Ko, Cheng-Ta; Yang, Henry; Lau, John H.; Li, Ming; Li, Margie; Lin, Curry; Lin, J. W.; Chen, Tony; Xu, Iris; Chang, Chieh-Lin; Pan, Jhih-Yuan; Wu, Hsing-Hui; Yong, Qing Xiang; Fan, Na; Kuah, Eric; Li, Zhang; Tan, K. H.; Cheung, Yiu-ming; Ng, Eric; Wu, Kai; Hao, Ji; Beica, Rozalia; Lin, Marc; Chen, Y-H.; Zhong, Cheng; Wee, Koh Sau; Jiang, Runqing; Cao, Xi; Lim, Sze Pei; Nc, Lee; Tao, Mian; Lo, Jeffery C. C.; Lee, S. W. Ricky

doi:10.1109/ectc.2018.00061

Cited by 25 publications

(3 citation statements)

References 9 publications

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“…In this case, one shot, it can produce 629 10 mm Â 10 mm packages. Figure 7 shows a special process flow of chip-first with die face-down with a panel carrier [48][49][50]. Since the panel carrier involves the PCB process, the work must be done on the device wafer by electroplating an 8-lm Cu-pad on top of the Al-pad.…”

Section: (C)mentioning

confidence: 99%

“…The Cu contact-pad is 110 lm in diameter and is 8 lm tall from the Al-pad. Figure 10 shows a panel carrier of 340 mm Â 340 mm with 378 (10 mm Â 10 mm) packages [48,49]. Figure 11 shows a panel carrier of 508 mm Â 508 mm with 1512 (10 mm Â 10 mm) packages [50].…”

Section: (C)mentioning

confidence: 99%

“…Figure 32 shows a semi-additive process (SAP) flow for fabricating the RDLs on a panel published in Refs. [48][49][50]. It starts off by laminating an Ajinomoto buildup film (ABF) on the reconstituted ECM-panel.…”

Section: Redistribution Layers By Pure Printed Circuit Board Technolomentioning

confidence: 99%

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Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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Section: (C)mentioning

confidence: 99%