Chiplet Heterogeneous Integration

Lau, John H.

doi:10.1007/978-981-16-1376-0_9

Cited by 11 publications

(5 citation statements)

References 48 publications

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“…Among the prominent packaging technologies are (see Figure 3): 2D Packaging: This approach involves directly integrating multiple chips on a packaging substrate, resembling a miniature PCB. Utilizing methods such as fan-out/fan-in waferlevel packaging and narrow pitch wire bonds, 2D SiP [32] offers increased integration capabilities and a smaller form factor, making it well-suited for portable devices like smartphones, tablets, and smartwatches. 2.1D Packaging: 2.1D packaging [33] employs an ultra-highdensity redistribution layer (RDL) situated between thin-film layers, characterized by precise metal line width and spacing.…”

Section: Overview Of Sip Architecturementioning

confidence: 99%

“…Intel's Foveros [36] is a noteworthy example of 3D packaging, where different functional dies are stacked using TSVs and micro-bumps. Among these technologies, 2.5D packaging has gained more popularity as it balances various factors, including enhanced performance via shorter interconnect lengths, efficient high-bandwidth communication via TSVs, improved power efficiency, form factor optimization, and capacity for a wider range of applications and design complexity than other packaging technologies [32], and accordingly, in this study, we consider the more generic 2.5D SiP structure for our implementation and evaluation.…”

Section: 5d Packagingmentioning

confidence: 99%

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Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Sami,

Zhang,

Shuvo

et al. 2024

IEEE Access

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The semiconductor industry has adopted heterogeneous integration (HI), incorporating modular intellectual property (IP) blocks (chiplets) into a unified system-in-package (SiP) to overcome the slowdown in Moore's Law and Dennard scaling and to respond to the increasing demand for advanced integrated circuits (ICs). Despite the manifold benefits of HI, such as enhanced performance, reduced area overhead, and improved yield, this transformation has also led to security vulnerabilities in the SiP supply chain and in-field operations, ranging from chiplet piracy and SiP reverse engineering (RE) to information leakage. Although conventional countermeasures provide the desired robustness for monolithic ICs, they are insufficient for addressing these challenges in the context of HI. To address these concerns, this paper presents a novel root-of-trust architecture, augmenting the process of integration using a centralized chiplet hardware security module (CHSM), aiming to provide comprehensive and robust protection throughout the SiP supply chain and in-field operations. Also, the proposed architecture equipped with the CHSM effectively addresses potential security breaches while providing robust protection against zero-day attacks through its reconfigurable capabilities. Throughout five detailed case studies, this paper performs a comprehensive security analysis to illustrate the resilience of CHSM against contemporary attack scenarios in the HI domain.

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Section: Overview Of Sip Architecturementioning

confidence: 99%

Section: 5d Packagingmentioning

confidence: 99%

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration

Sami,

Zhang,

Shuvo

et al. 2024

IEEE Access

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“…With advanced packaging, it has proven possible to maintain high performance even while separately fabricating parts of circuits that previously had been fully integrated into a single die. 90,91) This is currently being done to improve the cost-effectiveness of advanced lithography. 92) For example, the high performance logic circuits of AMD's Epyc processor have been fabricated using 7 nm technology, while input/output functions were fabricated using lower cost 14 nm processes.…”

Section: Solutions For Large Diesmentioning

confidence: 99%

High-NA EUV lithography: current status and outlook for the future

Levinson¹

2022

Jpn. J. Appl. Phys.

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High-NA extreme ultraviolet (EUV) lithography is currently in development. Fabrication of exposure tools and optics with a numerical aperture (NA) equal to 0.55 has started at ASML and Carl Zeiss. Lenses with such high NA will have very small depths-of-focus, which will require improved focus systems and significant improvements in wafer flatness during processing. Lenses are anamorphic to address mask 3D issues, which results in wafer field sizes of 26 mm × 16.5 mm, half that of lower NA EUV tools and optical scanners. Production of large die will require stitching. Computational infrastructure is being created to support high-NA lithography, including simulators that use Tatian polynomials to characterize the aberrations of lenses with central obscurations. High resolution resists that meet the line-edge roughness (LER) and defect requirements for high-volume manufacturing (HVM) also need to be developed. High power light sources will also be needed to limit photon shot noise.

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“…With the advance of heterogeneous integration, these differently manufactured discrete chiplets can be placed in the same package on a passive or active silicon interposer [7], [8], [9] which allows high-speed connection between chiplets, unlike in SiP architectures with organic interposers [10], [11].…”

Section: Introductionmentioning

confidence: 99%