Circuit optimization using statistical static timing analysis

Abstract

In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is difficult to capture the quality of a distribution with a single metric. Hence, we first introduce a new objective function that provides an effective measure for the quality of a delay distribution for both ASIC and high performance designs. We then propose an efficient and exact sensitivity based pruning algorithm based on a newly proposed theory of perturbation bounds. A heuristic approach for sensitivity computation which relies on efficient computation of statistical slack is then introduced. Finally, we show how the pruning and statistical slack based approaches can be combined to obtain nearly identical results compared with the brute-force approach but with an average run-time improvement of up to 89x. We also compare the optimization results against that of a deterministic optimizer and show an improvement up to 16% in the 99-percentile circuit delay and up to 31% in the standard deviation for the same circuit area.

New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits

“…However, in practice, complete and exact statistical information is not always available or might be difficult to obtain from the foundries. In [15] a method for worst-case estimation of timing-yield that deals with those difficulties is presented. This method is based on distributional robustness theory (DRT).…”

Statistical lifetime reliability optimization considering joint effect of process variation and aging

“…Gate sizing technologies [9][10][11] based on statistical static timing analysis were proposed to mitigate the PV-induced uncertainty on circuit timing. Teodorescu et al [12] proposed dynamic fine-grain body biasing to reduce the leakage power under PV effect.…”

“…The worst delay degradations on these gates can then be obtained using Eq. (9) given the worst duty cycles.…”

“…All of the statistically critical gates are sorted into a candidate group in descendent order based on their P g 's. Similar with [8][9][10], the sizing operation in each iteration can be performed on multiple gates at the same time for the runtime consideration. It picks the first n gates from the candidate group and sizes PMOSs and NMOSs lying on the statistically critical paths simultaneously by increasing a unit width on them.…”

“…The SþC sizing method was proposed in [8], which sizes gate by jointly considering sensitivity and criticality of the gate. The SþD sizing method is derived from the traditional sizing method such as that was used in [9][10][11]. It considers both sizing sensitivity and practical delay degradation of the gate while without taking criticality of the gate into account.…”