Circuit placement, chip optimization, and wire routing for IBM IC technology

Hathaway, D.J.; Habra, R. R.; Schanzenbach, E. C.; Rothman, S. J.

doi:10.1147/rd.404.0453

Cited by 10 publications

(3 citation statements)

References 9 publications

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“…In addition, short electrical interconnection offers high density, high speed, and low switching energy with respect to the local distribution of a clock signal. The ability to place and route automatically local clock interconnection using computer-aided design tools additionally compliments the advantages of short electrical interconnection [60]- [62]. Thus, the local portion of any optical clock distribution network will likely be realized through electrical interconnect, and the requirement for a global fanout on the order of the number of local latches does not exist.…”

Section: Strengths and Weaknesses Of Optical Clock Distributionmentioning

confidence: 99%

Electrical and optical clock distribution networks for gigascale microprocessors

Mule

Glytsis

Gaylord

et al. 2002

IEEE Trans. VLSI Syst.

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A summary of electrical and optical approaches to clock distribution within high-performance microprocessors is presented. System-level properties of intrachip electrical clock distribution networks corresponding to three microprocessor families are summarized. It is found that global clock interconnect performance and short-term jitter present the greatest challenges to the continued use of conventional clock distribution methodologies. An extrapolation of trends describing the percentage of clock period consumed by global skew and short-term jitter identifies the 32-nm technology generation of the 2002 International Technology Roadmap for Semiconductors (ITRS) as the first technology generation within which alternate methods of clock distribution may be warranted. Research efforts investigating interboard through intrachip optical clock distribution are also summarized. An optical distribution network compatible with high volume manufacturing in conjunction with a suitable means of providing optical-to-electrical signal conversion comprise the two fundamental challenges facing successful implementation of an optical clock distribution network. It is found that a global guided-wave distribution capable of efficient input and output coupling of optical power is required to meet the first challenge. The identification of a suitable means of optical-to-electrical conversion, however, remains an active topic of research.Index Terms-High performance, high-speed interconnect, optical, optoelectronic integrated circuits, system level, VLSI.

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Section: Strengths and Weaknesses Of Optical Clock Distributionmentioning

confidence: 99%

Electrical and optical clock distribution networks for gigascale microprocessors

Mule

Glytsis

Gaylord

et al. 2002

IEEE Trans. VLSI Syst.

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“…As clock frequencies increased and interconnect delay became significant, clock distribution became an important issue. A variety of techniques were developed to generate delay-balanced routing of clock nets [90], [91], and to optimize the assignment of clock sinks to nets in buffered clock trees [92]. Initially, buffered clock tree generation was done using simulated annealing.…”

Section: ) Placementmentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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“…This is accomplished using IBM CO2, a tool that traverses the clock trees, identifying and reconfiguring equivalent nets as well as adding parallel copies of buffers to minimize clock skew [1]. The LCBs at the leaf nodes of the clock tree are placed at the RC centroid of the latch cluster to minimize RC induced skews.…”

Section: Figure 4 Timing Driven Design Iterationmentioning

confidence: 99%

A pseudo-hierarchical methodology for high performance microprocessor design

Bertolet¹,

Carpenter²,

Carrig³

et al. 1997

Proceedings of the 1997 International Symposium on Physical Design - ISPD '97

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-This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for design control, algorithmic power grid generation, fully customized clock network insertion, timing driven placement and routing, an integrated timing closure strategy, and incremental checking that includes formal netlist verification, DRC and LVS. The methodology places particular emphasis on continuously improving the integration process and incrementally improving both the design and the interoperability of the tools. The final chip tape-out was 17 calendar days from the final netlist.

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Circuit placement, chip optimization, and wire routing for IBM IC technology

Cited by 10 publications

References 9 publications

Electrical and optical clock distribution networks for gigascale microprocessors

Electrical and optical clock distribution networks for gigascale microprocessors

EDA in IBM: past, present, and future

A pseudo-hierarchical methodology for high performance microprocessor design

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