Circuit techniques for large CSEA SRAMs

Abstract

The CMOS-storage emitter-access (CSEA) memory cell offers faster access than the MOS cells used in conventional BiCMOS SRAM'S, but using it in large memory arrays poses several problems. This paper describes novel BiCMOS circuit approaches to address the problems of decoding power, electronic noise, level translation, and write disturbance. It also reports results on a 64-kb CSEA SRAM using these techniques. The device, fabricated in a 0.8-~m BiCMOS technology, achieves read access and write pulse times of less than 4 ns while dissipating 1.7 W at a case temperature of 70"C.

A 1.3-ns 32-word by 32-bit three-port BiCMOS register file

“…Fig. 7 shows the level converter [3] and its associated reference circuitry. The output level of the unselected decoders is 0 V, which keeps transistor P1 OFF.…”