Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

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“…This means that advanced p-MTJs and advanced cell structure designs are critical for normally off computers. 30,37,38 IV. CPU CORE…”

Section: Energy Saving and Performance Of P-mtj Based Llcmentioning

confidence: 99%

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

Ando¹,

Fujita²,

Ito³

et al. 2014

Journal of Applied Physics

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112

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“…7. 3T-3MTJ STT-MRAM cell: A 3T-3MTJ cell structure was formed by combining the 2T-2MTJ and 1T-1MTJ STT-MRAM cell architectures to urge the advantages of both cell structures 15 as delineated in Figure 2G. A cell can store 2-bit information with suitable mapping from information to MTJ states.…”

Section: Conventional Stt-mram Cell Architecturesmentioning

confidence: 99%

“…Other cell structures like 3T-2MTJ, 4T-4MTJ, and 4T-2MTJs are introduced in several studies. 11,15,16 All the standard STT-MRAM cell architecture as described above confronts excessive power requirements and significant latency throughout the write operation. Also, some of the cells present poor writability and read stability.…”

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confidence: 99%

Novel low‐power and stable memory cell design using hybrid CMOS and MTJ

Prasad¹,

Sahu²,

Mandi³

et al. 2021

Circuit Theory & Apps

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Memory is an essential component of any VLSI data storage system. Because of the shrinking of CMOS processing nodes, power consumption in conventional memory (SRAM and DRAM) increases. Traditional memory technologies also suffer several additional difficulties, such as limited scalability, low reliability, short data retention time, low durability, increased space, and latency, among others. As a result, new device technologies are critical for developing low-power, high-performance memory devices. Among the numerous developing nonvolatile (NV) memory technologies available today, STT-MRAM is regarded as one of the most appealing and promising NV memory technologies for overcoming the limitations of traditional memories. STT-MRAM is more efficient, quicker, NV, highly scalable, and readily integrated with CMOS technology. Because of the scalability of technology nodes below 45 nm, traditional STT-MRAM cells have several difficulties, including high write power consumption, destructive read and write operation, prolonged write time, and so on. To address the issues associated with the writing operation of STT-MRAM cells, this article presented an optimum STT-MRAM cell design based on PMA-MTJ. The write failure mitigation strategies are utilized to increase the proposed cell's write stability. A comparative analysis between conventional STT-MRAM cell and the proposed cell is performed by concerning the write power consumption, write delay, and write stability. The experimental results indicate the performance superiority of the proposed cell architecture.IP (in-plane), MTJ (magnetic tunnel junction), PMA (perpendicular magnetic anisotropy), STT-MRAM, write margin, write power | INTRODUCTIONSemiconductor memory devices and technologies, such as memory storage, are critical for data storage in electronics. Memory currently occupies more than 80% of the die area. This percentage is constantly increasing due to the continued reduction of the CMOS technology node below the 90-nm domain. Memory performance rises in terms of size and speed owing to technological scaling, while the static power consumption of CMOS-based memories increases due to an exponential growth in standby current. 1 Memory reliability is also impacted. The length of global interconnects

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“…目前已有诸多的STT-MRAM测试芯片和商用产品问世. 表2 [11,[111][112][113][114][115][116][117][118][119][120][121][122][123][124][125][126][127][128] 列举了近年来学术界和工业界在该领表 2 近年来的STT-MRAM芯片性能指标 Univ Toronto/Fujitsu Lab [111] 16 Kbit 130 cell: 5.525 R: 9, W: 9-10 a) W: 0.4-0.87 mA 2010 Toshiba [112] 64 Mbit 65 cell: 0.3584, Die: 47.124 30 R: 10 μA, W: 49 μA 2010 Hynix/Grandis [113] 64 Mbit 54 Cell: 0.041 R: <20 W: 140 μA…”

Section: 随着磁隧道结制备工艺的改进和电路性能的优化unclassified

“…Hitachi/Univ Tohoku [114] 32 Mbit 150 cell: 1, chip: 94.83 R: 32, W: 40 W: 300 μA 2010 IBM [115] 4 Kbit array -W: 50 W:~200 μA 2011 Qualcomm [116] 1 Mbit 45 cell: 0.1026, chip: 0.27 R: 10 -2012 Everspin [32,117] 64 Mbit 90 -10~50 -2013 TSMC [118] 1 Mbit 40 macro: 0.56 mm 2 R: 10 W: 281-283 μA 2013 NEC/Univ Tohoku [119] 1 Toshiba [121] 512 Kbit 65 cell: 0.504 8 R: 4 mW, W: 15 mW 2013 Toshiba [122] 1 Mbit 65 cell: 0.45 R: 4, W: 4 R: 0.142 nJ, W: 0.372 nJ 2013 Infineon/TUM [123] 8 Mbit 40 -R: 23 -2014 TDK-Headway [124] 8 Mbit 90 cell: 0.4 W: <5, R: 4 -2015 IBM [125] 4 Kbit array -W: 20-50 -…”

mentioning

confidence: 99%

Recent progresses in spin transfer torque-based magnetoresistive random access memory (STT-MRAM)

Zhao¹,

Wang²,

Peng³

et al. 2016

Sci. Sin.-Phys. Mech. Astron.

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Circuit techniques in realizing voltage-generator-less STT MRAM suitable for normally-off-type non-volatile L2 cache memory

Cited by 13 publications

References 5 publications

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

Novel low‐power and stable memory cell design using hybrid CMOS and MTJ

Recent progresses in spin transfer torque-based magnetoresistive random access memory (STT-MRAM)

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