Circuits and System Design of RF Polar Transmitters Using Envelope-Tracking and SiGe Power Amplifiers for Mobile WiMAX

Li, Yan; Lopez, Jerry; Lie, Donald Y. C.; Chen, K; Wu, S.F.; Yang, Tzong–Jer; Ma, Gin-Kou

doi:10.1109/tcsi.2010.2089562

Cited by 51 publications

(9 citation statements)

References 26 publications

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“…In addition, the efficiency variation becomes less dependent on the once the envelope clipping is applied. A CR of 1.6 dB for the LTE signal is experimentally determined for best efficiency with very little linearity degradation [8], [29]. Fig.…”

Section: B Evaluation Of the Bcd Envelope Modulator With Sige Pamentioning

confidence: 98%

“…When the is increased from 3.5 V to 7 V, the envelope waveform is kept with the same clipping ratio (CR) during testing. The clipping ratio in this work is defined as (2) where denotes the peak of the ideal output envelope, and is the clipping level due to the rail-to-rail limitation of the envelope modulator [8], [29]. As shown in Fig.…”

Section: B Evaluation Of the Bcd Envelope Modulator With Sige Pamentioning

confidence: 99%

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Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

Lopez

Schecht

et al. 2012

IEEE J. Solid-State Circuits

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This paper presents the design insights for the implementation of a fully monolithic radio frequency (RF) power amplifier (PA) using both envelope-tracking (ET) and transistor resizing techniques for long-term evolution (LTE) applications. At the low output power region, some of the power cells in the PA can be disabled to further save power consumption, thus enhancing the efficiency from a traditional ET-PA. Our ET-PA system is first realized with a two-chip solution, consisting of a high voltage envelope modulator fabricated in a 0.35 m Bipolar-CMOS-DMOS (BCD) technology, and a differential cascode PA in a 0.35 m SiGe BiCMOS technology. This two-chip solution of the ET-PA is to showcase the effective efficiency enhancement of using the transistor resizing method. In the second design, a CMOS envelope modulator is integrated with the cascode PA on the same die in the 0.35 m SiGe BiCMOS technology. Some insights are demonstrated regarding the optimization of the envelope modulator specific to our cascode PA for LTE broadband signals, where the finite bandwidth and the switching frequency of the envelope modulator are considered for achieving the minimal error-vector magnitude (EVM) and spurious noise. The fully monolithic BiCMOS ET-PA reaches the maximum linear output power ( ) of 24 dBm and 23.4 dBm with overall power-added-efficiency (PAE) of 41% and 38% for the LTE 16QAM 5 MHz and 10 MHz signals at 1.9 GHz, respectively, without needing predistortion. At the low power mode of our ET-PA, an additional PAE enhancement of 4% is obtained at of 16-20 dBm by disabling some of the PA power cells. Our fully monolithic ET-PA satisfies the LTE 16QAM linearity specs with high efficiency. Index Terms-Bipolar-CMOS-DMOS (BCD), cascode power amplifier (PA), envelope modulator, envelope-tracking (ET), long-term evolution (LTE), low power mode, SiGe BiCMOS, transistor resizing.

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Section: B Evaluation Of the Bcd Envelope Modulator With Sige Pamentioning

confidence: 98%

Section: B Evaluation Of the Bcd Envelope Modulator With Sige Pamentioning

confidence: 99%

Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

Lopez

Schecht

et al. 2012

IEEE J. Solid-State Circuits

Self Cite

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“…Even so, as a power amplifier is also indispensable in many other important applications such as radar system [4], base station [5], etc., researchers turned to SiGe power amplifier [6], since it not only is superior to CMOS power amplifier on frequency response and power gain, but also can be integrated well with CMOS technology while its speed and power performance have been comparable to GaAs technology. So the SiGe power amplifier has attracted much research interest in this field [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Design of 900 MHZ Sige Power Amplifier With Linearization Bias Circuit

Zhang¹,

Zhang²,

Fu³

et al. 2016

PIER C

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Abstract-A single stage 900 MHz power amplifier (PA) with linearization bias circuit is designed with HHNEC 0.5 µm BIS500G power SiGe BiCMOS process. It is implemented by single-ended common emitter structure as a class AB power amplifier. The adopted active bias circuit is originally explained by using two virtue current sources, so that the mechanism of the improvement of linearity can be described more clearly. Then the mechanism is applied to guide the design of a power amplifier with an active bias circuit, which shows better linearity than resistor biased power amplifier by simulation. Through further design and measurement, the fabricated single stage power amplifier exhibits output power 1 dB compression point (OP1 dB) of 18.9 dBm, with power added efficiency (PAE) of 26.75% and power gain of 20.9 dB under 3.3 V voltage supply.

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“…Even by compensating for the nonlinear distortion using digital predistortion (DPD) [5], the power efficiency improvement that can be achieved is limited. To significantly improve the power efficiency figures, dynamic supply modulation techniques, such as envelope tracking (ET) [6], have been proposed in dual-band systems [7]- [11].…”

Section: Introductionmentioning

confidence: 99%

3-D Distributed Memory Polynomial Behavioral Model for Concurrent Dual-Band Envelope Tracking Power Amplifier Linearization

Gilabert

Montoro

2015

IEEE Trans. Microwave Theory Techn.

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Abstract-This paper presents a new three-dimensional (3D) behavioral model to compensate for the nonlinear distortion arising in concurrent dual-band (DB) Envelope Tracking (ET) Power Amplifiers (PAs). The advantage of the proposed 3D distributed memory polynomial (3D-DMP) behavioral model, in comparison to the already published behavioral models used for concurrent dual-band envelope tracking PA linearization, is that it requires a smaller number of coefficients to achieve the same linearity performance, which reduces the overall identification and adaptation computational complexity. The proposed 3D-DMP digital predistorter (DPD) is tested under different ET supply modulation techniques. Moreover, further model order reduction of the 3D-DMP DPD is achieved by applying the principal component analysis (PCA) technique. Experimental results are shown considering a concurrent DB transmission of a WCDMA signal at 1.75 GHz and a 10 MHz bandwidth LTE signal at 2.1 GHz. The performance of the proposed 3D-DMP DPD is evaluated in terms of linearity, drain power efficiency and computational complexity.

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Circuits and System Design of RF Polar Transmitters Using Envelope-Tracking and SiGe Power Amplifiers for Mobile WiMAX

Cited by 51 publications

References 26 publications

Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications

Design of 900 MHZ Sige Power Amplifier With Linearization Bias Circuit

3-D Distributed Memory Polynomial Behavioral Model for Concurrent Dual-Band Envelope Tracking Power Amplifier Linearization

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