Circuits and techniques for high-resolution measurement of on-chip power supply noise

Abstract

A technique for characterizing the cyclically time varying statistical properties and spectrum of power supply noise using only two on-chip samplers is presented. The samplers utilize a voltage-controlled oscillator to perform highresolution analog-to-digital conversion with minimal hardware. The measurement system is implemented in a 0.13pm process as part of a high-speed link transceiver.Measurement results showing the cyclostationary behavior of power supply noise are presented.

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs

“…Other studies model the supply as a slow sinusoid in the 100-500MHz range [25] to model resonance in the grid with a ±5% peak-to-peak swing. Other work measured power supply noise and found a mixture of deterministic noise caused by the clock signal and its harmonics, random cyclostationary noise caused by switching logic, and random high frequency white noise [26]. Compared to ASICs, FPGAs have a slower user clock, larger interconnect capacitance driven by strong buffers, and more disperse logic.…”

Power Supply Rejection for RF Amplifiers: Theory and Measurements

“…The first-order transfer function for the system in Fig. 2 is solved as (13) where is the admittance of the source degeneration. The term is a dummy frequency variable that represents the frequency content of the input signal [4], [25].…”

“…However, large values of source degeneration increase the contribution of second order transconductance parameters and . Following the derivation of (4) and (10), the PSRR can be written as dB , in which case many of the terms in (13) and (19) are cancelled. The resulting expression for the CMOS amplifier follows as dB (24) In (24), the denominators in the expressions for and are cancelled.…”

“…In the layout, common sources of supply noise include magnetic coupling to bond wires and power supply interconnect, electrostatic coupling between nearby traces, and current noise from analog or digital blocks passing through parasitic inductance and resistance in the power rails [13]. Supply noise may also be directly injected into the system by the voltage regulator [14]- [21].…”

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance

“…1 for a synchronous digital circuit. A significant number of registers switches simultaneously with the rising edge of the clock, causing a considerable drop in the power supply voltage during this transition time [5]. Furthermore, the noise signal can propagate to the output of a gate, degrading signal integrity and causing unnecessary power consumption [6], [7].…”