Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Elshazly, Amr; Inti, Rajesh; Young, Ben; Hanumolu, Pavan Kumar

doi:10.1109/jssc.2013.2254552

Cited by 79 publications

(38 citation statements)

References 18 publications

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“…Compared with DLL with frequency multiplier architectures, the proposed clock generator shows the superior performance according to both FoM1 and FoM2, as expected. Note that both the multiplying DLL and the PLL architecture in [18] show superior performance than the proposed clock generator in FoM1. Even the area and the multiplication ratio are considered using FoM2, the multiplying DLL in [18] is still shows better performance than the proposed clock generator.…”

Section: Measurement Resultsmentioning

confidence: 99%

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Ryu

Jung

et al. 2016

IEEE Trans. VLSI Syst.

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A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive-and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-µm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz-3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 µW/MHz. Index Terms-Clock generator, delay-locked loop (DLL), edge combiner, frequency multiplier.

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Section: Measurement Resultsmentioning

confidence: 99%

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Ryu

Jung

et al. 2016

IEEE Trans. VLSI Syst.

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“…Compared to a PLL, an MDLL offers superior phase noise due to the periodic reference injection and consumes low power due to relaxed phase noise requirements of the oscillator [18]- [20]. The block diagram of the digital MDLL is shown in Fig.…”

Section: E High-frequency Reference Generationmentioning

confidence: 99%

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Nandwana

Anand

Saxena

et al. 2015

IEEE J. Solid-State Circuits

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A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of 104 dBc/Hz and 1.5 ps integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of 225.8 dB.Index Terms-Calibration-free, delta-sigma modulator, fractional-N PLL, frequency synthesizer, multiplying delay-locked loop (MDLL), phase interpolator (PI), phase noise, phase-locked loop (PLL), quantization error cancellation, ring-VCO. 0018-9200

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“…The first stage implemented using a digital multiplying DLL (MDLL) [21] multiplies a 50 MHz crystal oscillator output and generates a 500 MHz output clock that acts as the reference clock to the second stage ΔΣ fractional-N PLL. Because oversampling ratio of the ΔΣ modulator is increased by a factor of 10, the PLL bandwidth can be increased to adequately suppress ring oscillator phase noise without increasing the contribution of ΔΣ truncation error to output jitter [20], [22].…”

Section: B Digitally Controlled Oscillatormentioning

confidence: 99%

“…The digital MDLL is adopted for reference multiplication due to its superior phase noise performance compared to a conventional PLL [21], [23]. As shown in Fig.…”

Section: B Digitally Controlled Oscillatormentioning

confidence: 99%

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

Shu

Choi

Saxena

et al. 2016

IEEE J. Solid-State Circuits

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A continuous-rate digital clock and data recovery (CDR) with automatic frequency acquisition is presented. The proposed automatic frequency acquisition scheme implemented using a conventional bang-bang phase detector (BBPD) requires minimum additional hardware, is immune to input data transition density, and is applicable to subrate CDRs. A ring-oscillatorbased two-stage fractional-N phase-locked loop (PLL) is used as a digitally controlled oscillator (DCO) to achieve wide frequency range, low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ring oscillator noise suppression in conventional CDRs. The CDR is implemented using a digital D/PLL architecture to decouple JTRAN bandwidth from jitter tolerance (JTOL) corner frequency, eliminate jitter peaking, and remove JTRAN dependence on BBPD gain. Fabricated in a 65 nm CMOS process, the prototype CDR achieves error-free operation (BER < 10 −12 ) from 4 to 10.5 Gb/s with pseudorandom binary sequence (PRBS) data sequences ranging from PRBS7 to PRBS31. The proposed automatic frequency acquisition scheme always locks the CDR loop within 1000 ppm residual frequency error in worst case. At 10 Gb/s, the CDR consumes 22.5 mW power and achieves a recovered clock long-term jitter of 2.2 ps rms/24.0 pspp with PRBS31 input data. The measured JTRAN bandwidth and JTOL corner frequencies are 0.2 and 9 MHz, respectively.Index Terms-Active repeater, automatic frequency acquisition, continuous-rate receivers, decouple jitter transfer (JTRAN)/jitter generation (JGEN), decouple JTRAN/jitter tolerance (JTOL), digital clock and data recovery (CDR), fractional-N phase-locked loop (PLL), high-speed serial link, jitter peaking, multiplying delaylocked loop, optical links, reference-less frequency-locked loop, supply regulator, wide-range digitally controlled oscillator (DCO).

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Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Cited by 79 publications

References 18 publications

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

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