Clustering and pattern matching for an automatic hotspot classification and detection system

Ghan, Justin; Ma, Ning; Mishra, Sandipan; Spanos, Costas J.; Poolla, Kameshwar; Rodriguez, Norma; Capodieci, Luigi

doi:10.1117/12.814328

Cited by 28 publications

(28 citation statements)

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“…Work in [73] applies clustering techniques to test-response data collected from a large number of failing ICs to identify common failure signatures, which may indicate the presence of systematic issues. The work described in [83,84] performs extensive lithography simulation on the entire layout to identify hotspots.…”

Section: Prior Workmentioning

confidence: 99%

“…The work in [83,84] resembles LASIC but there are several important differences. First, [83,84] relies on simulation, which can be inaccurate and too conservative, i.e., it is likely to identify features that may never cause an IC to fail.…”

Section: Our Contributionmentioning

confidence: 99%

“…First, [83,84] relies on simulation, which can be inaccurate and too conservative, i.e., it is likely to identify features that may never cause an IC to fail. Fixing most (if not all) of the hotspots might result in over-correction which can adversely affect chip area and performance.…”

Section: Our Contributionmentioning

confidence: 99%

“…In addition, the work in [83,84] requires the entire design to be simulated. This limits the scalability of the methodology, especially when many different process corners are considered.…”

Section: Our Contributionmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Section: Prior Workmentioning

confidence: 99%

Section: Our Contributionmentioning

confidence: 99%

Section: Our Contributionmentioning

confidence: 99%

“…In addition, the work in [83,84] requires the entire design to be simulated. This limits the scalability of the methodology, especially when many different process corners are considered.…”

Section: Our Contributionmentioning

confidence: 99%

See 2 more Smart Citations

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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“…Several works [6][7][8][9][10][11][12][13] used various techniques of machine learning or fuzzy pattern matching to identify the hotspots in the design. References 14 and 15 suggested a flow that integrates a pattern checker, a pattern fixer, and a router, such that the router completes its job, then the pattern check and fix are performed if needed, and some routes are tentatively redone.…”

Section: Prior Workmentioning

confidence: 99%

Layout pattern-driven design rule evaluation

Badr

Gupta

2014

SPIE Proceedings

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Abstract. With the use of subwavelength photolithography, some layouts can have low printability and, accordingly, low yield due to the existence of bad patterns even though they pass design rule checks. A reasonable approach is to select some of the candidate bad patterns as forbidden. These are the ones with a high yield impact or low routability impact, and these are to be prohibited in the design phase. The rest of the candidate bad patterns may be fixed in the postroute stage in a best-effort manner. The process developers need to optimize the process to be friendly to the patterns of high routability impact. Hence, an evaluation method is required early in the process to assess the impact of forbidding layout patterns on routability. We propose pattern-driven design rule evaluation (pattern-DRE), which can be used to evaluate the importance of patterns for the routability of the standard cells and, accordingly, select the set of bad patterns to forbid in the design. The framework can also be used to compare restrictive patterning technologies [e.g., litho-etch-litho-etch (LELE), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned octuple patterning (SAOP)]. Given a set of design rules and a set of forbidden patterns, pattern-DRE generates a set of virtual standard cells; then it finds the possible routing options for each cell without using any of the forbidden patterns. Finally, it reports the routability metrics. We present a few studies that illustrate the use cases of the framework. The first study compares LELE to SADP by using a set of forbidden patterns that are allowed by LELE but not by SADP. Another study compares LELE to extreme ultraviolet lithography from the routability aspect by prohibiting patterns that have LELE native conflicts. In addition, we present a study that investigates the effect of placing the active area of the transistors close to the P/N interface instead of close to the power rails.

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Lithography hotspot detection and mitigation in nanometer VLSI

Gao

Ding

et al. 2013

2013 IEEE 10th International Conference on ASIC

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Abstract-With continued feature size scaling, even state of the art semiconductor manufacturing processes will often run into layouts with poor printability and yield. Identifying lithography hotspots is important at both physical verification and early physical design stages. While detailed lithography simulations can be very accurate, they may be too computationally expensive for full-chip scale and physical design inner loops. Meanwhile, pattern matching and machine learning based hotspot detection methods can provide acceptable quality and yet fast turn-around-time for full-chip scale physical verification and design. In this paper, we discuss some key issues and recent results on lithography hotspot detection and mitigation in nanometer VLSI.

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Clustering and pattern matching for an automatic hotspot classification and detection system

Cited by 28 publications

References 0 publications

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Layout pattern-driven design rule evaluation

Lithography hotspot detection and mitigation in nanometer VLSI

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