CMOS 8b 25MHz flash ADC

From measurements of the vertical sea level muon spectrum reported earlier this year by Ayre et al, the exponent of the production spectrum of the muons' parents has been calculated. As muon parents, pions and kaons decaying via the Kf12 mode only have been considered. There is an indication of a decrease in the value of the exponent of the pion production spectrum for E, > 100GeV which supports the suggestion of a flattening of the primary cosmic ray spectrum in the region 1012-1015 eV made by Wdowczyk and Wolfendale in 1973.

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“…The T/H circuit 18) and the ADC 19) are operated using the adjusted sampling clock (CK 1 -CK 3 ). The T/H circuit, as shown in Fig.…”

Section: T/h Circuit and Adcmentioning

confidence: 99%

Confocal Imaging System Using High-Speed Sampling Circuit and Ultra-Wideband Slot Antenna

Toya

Sasaki

Kubota

et al. 2011

Jpn. J. Appl. Phys.

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“…This is accomplished by incorporating nonoverlapped clock phases as shown in Fig. 11 [27], [28]. The auto-zero switches of the first stage are opened on clock AZ1; its charge injection offset is then amplified and stored on the next stage before the end of the next auto-zero period AZ2.…”

Section: Comparator Designmentioning

confidence: 99%

An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC

Nakamura

Hotta

Carley

et al. 1995

IEEE J. Solid-State Circuits

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The design of a low-power 10 b, 40 Msamplds ADC integrated in a 0.8 pm multithreshold CMOS process is presented. The h l l y differential design employs parallel-pipelined ADC each Using a combination of single-and multibit-per-stage pipelined archit".The ADC, targeted for high-resolution video terminals and ultrasound SCBnning applications, achieves a nonlinearity-plus-quantizationerror of fl LSB at 10 b, dissipates 85 mW from a single 2 7 V supply, and occupies an area of 1.9 m m by 2.1 mm.

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Analysis of reference‐tap‐voltage fluctuation in flash A/D converter

Nakaya

Kumamoto

Miki

et al. 1987

Electron Comm Jpn Pt II

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To improve the speed and accuracy of the CMOS flash A/D converter using a copper‐type comparator, an analysis has been performed for the voltage variation at each reference terminal of the ladder resistor providing a reference voltage. A model has been developed in which the circuit made of the ladder resistor and the input capacitance of the comparator is treated as a distributed network. A theoretical formula is derived which analytically provides transient behavior of each reference terminal voltage due to change in the comparator. With this formula, it is found that the maximum error of the reference terminal voltage occurs when the input voltage is either 0 or V ref. The error decreases exponentially with reduction of ladder resistors and comparator input capacitances and with increase of time. It is found that the product of the ladder resistor and the comparator input capacitance between adjacent terminals must be less than 5 × 10−13 F.Ω in order to obtain an 8 bit A/D converter with 20 MS/s. Variation is decreased if the midpoint of the ladder resistor is fixed. For instance, when the midpoint is fixed, the product of the ladder resistor and the comparator input capacitance is allowed to increase up to 2 × 10−12 F.Ω.

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CMOS 8b 25MHz flash ADC

Cited by 11 publications

References 6 publications

Confocal Imaging System Using High-Speed Sampling Circuit and Ultra-Wideband Slot Antenna

Confocal Imaging System Using High-Speed Sampling Circuit and Ultra-Wideband Slot Antenna

An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC

Analysis of reference‐tap‐voltage fluctuation in flash A/D converter

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