CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors

Abstract

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Modeling and Design of High Bandwidth Feedback Loop for dv/dt Control in CMOS AGD for GaN

“…1 shows the transistor level schematics of the proposed CMOS AGD. As already demonstrated in [2] from the same authors, the dv/dt can be controlled by changing the value of the gain. The gain is made by the width ratios of transistors involved in a PMOS and a NMOS current mirrors.…”

“…Author version of the accepted article published in the IEEE ISPSD2020 proceedingshttps://doi.org/10.1109/ISPSD46842.2020.9170106 This work shows a step-by-step analytical analysis aimed to optimize the parameters of the circuit shown in Fig. 1, circuit previously presented in details in [2].…”

“…Switching times of wide bandgap power transistors are extremely high (hundreds of V/ns for 600V GaN or 1.2kV SiC MOSFET) [1]. Therefore, practical useful guidelines are provided to the designer to determine the best trade-off in terms of integrated high voltage capacitive dv/dt sensor (CS), current mirror gain and PMOS/NMOS transistors sizes in order to design an integrated dv/dt control system [2]- [4]. Systematic comparison between theoretical predictions and CADENCE TM simulation/layout use-case designs are investigated to demonstrate the validity of the approach.…”

Modular Multilevel SOI-CMOS Active Gate Driver Architecture for SiC MOSFETs

“…Other attempts for multilevel gate drivers have been presented in the literature, mainly with discrete solutions [4][5][6][7][8][9][10], while active gate drivers focused on improved switching loss -EMI tradeoff [11,12] or short circuit protection [13]. The core idea here is to cascade 5V CMOS push-pull circuits in series, each being supplied by the energy stored in 5V floating capacitors (Fig reduced to +12V during turn-on, the peak gate current is maintained high to guarantee high switching speeds and low SiC switching losses thanks to a lower gate resistance than the one in classical 2-level operation.…”

Full Custom Design of an Arbitrary Waveform Gate Driver With 10-GHz Waypoint Rates for GaN FETs

“…Here, the main challenge is to achieve sufficient analogue bandwidth, to make the power waveforms follow a reference waveform with nanosecond transient features, whilst maintaining an acceptable power consumption. Such closedloop techniques are beginning to be developed for GaN [13], however achieving the required speeds is a challenge, as some of the unwanted features in switching transients (such as the temporary inductive drop in drain-source voltage during turnon) have frequency components upwards of 10s of GHz [14].…”